LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 284

• Manufacturer Part Number: LFXP2-8E-5TN144I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5TN144I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 14-1. Programming Block Diagram
Configuration Pins
The LatticeXP2 has one dedicated and nine dual-purpose sysCONFIG pins. The dual-purpose pins are available
as extra I/O pins if they are not used for configuration.
The configuration mode pins, along with a programmable option, controls how the LatticeXP2 will be configured.
The configuration mode pins (CFG[1:0]) are generally hard wired on the PCB and determine which configuration
mode will be used; the programmable option is accessed via preferences in Lattice ispLEVER
as HDL source file attributes, and allows the user to protect the configuration pins from accidental use by the user
or the place-and-route software. The LatticeXP2 devices also support ispJTAG for configuration, including trans-
parent readback, and for JTAG testing. The following sections describe the functionality of the sysCONFIG and
JTAG pins. Note that JTAG and ispJTAG will be used interchangeably in this document. Table 14-1 is provided for
reference.
Table 14-1. Configuration Pins for the LatticeXP2 Device
CFG0
CFG1
PROGRAMN
INITN
DONE
CCLK
SISPI
SOSPI
CSSPISN
CSSPIN
TDI
TDO
TCK
Pin Name
Input, weak pull-up
Input, weak pull-up
Input, weak pull-up
Bi-Directional Open Drain, weak pull-up
Bi-Directional Open Drain with weak pull-up or Active Drive
Input or Output
Input or Output
Input or Output
Input, weak pull-up
Output, tri-state, weak pull-up
Input, weak pull-up
Output
Input with Hysteresis
Port
Mode
Memory Space
Program in seconds
ispJTAG 1149.1 TAP
Flash Memory
JTAG 1532
Space
I/O Type
microseconds
Program in
14-2
SDM
1
LatticeXP2 sysCONFIG Usage Guide
sysCONFIG Port
SRAM Memory
Master SPI
Slave SPI
Space
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dedicated
Pin Type
Program in
milliseconds
JTAG
JTAG
JTAG
2
2
2
2
®
design software, or
Mode Used
MSPI, SSPI
MSPI, SSPI
MSPI, SSPI
MSPI, SSPI
MSPI, SSPI
MSPI, SSPI
MSPI, SSPI
Master SPI
Slave SPI
All