LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 228

• Manufacturer Part Number: LFXP2-8E-5TN144I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5TN144I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 11-27. Input Register Block Configured as IDDRXC
Figure 11-28 shows the timing waveform when using the IDDRXC module.
Figure 11-28. IDDRXC Waveform
IDDRFXA
This primitive inputs DDR data at both edges of clock CLK1 and generates two streams of data aligned to clock
CLK2. CLK1 can be connected either to the edge clock or the internal FPGA clock. If the Edge clock input is used
for CLK1 then CLK2 should be generated from the same clock going to CLK1.
DDR DATA at IDDRXC
DDR DATA at I/O
CLK at IDDRXC
DATA
CLK at I/O
QA
QB
C
A
B
P0
P0
XX
XX
XX
XX
P0
N0
N0
B
A
DDR Registers
P0
N0
P1
P1
P1
P0
N0
N1
N1
11-24
IDDRXC
Edge Clock
C
N1
P1
P2
P2
LatticeXP2 High-Speed I/O Interface
N1
P2
P1
N2
N2
CLK
Synchronization
FPGA Clock
N2
P2
P3
Registers
P3
E
D
P3
P2
N2
N3
N3
N3
P3
P4
P4
P4
N3
P3
QB
QA
N4
N4
P4