LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 282

• Manufacturer Part Number: LFXP2-8E-5TN144I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5TN144I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Lattice XP2 sysDSP Usage Guide
parameter REG_INPUTB1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTB1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTB1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_INPUTB2_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTB2_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTB2_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_INPUTB3_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTB3_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTB3_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_PIPELINE0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_PIPELINE0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_PIPELINE0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_PIPELINE1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_PIPELINE1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_PIPELINE1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_PIPELINE2_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_PIPELINE2_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_PIPELINE2_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_PIPELINE3_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_PIPELINE3_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_PIPELINE3_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_OUTPUT_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_OUTPUT_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_OUTPUT_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDA_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDA_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDA_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDA_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDA_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDA_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDB_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDB_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDB_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDB_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDB_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDB_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB1_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB1_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB1_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB1_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB1_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB1_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB3_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB3_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB3_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB3_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB3_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB3_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter GSR = “ Enabled, Disabled “;
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