LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 145
LFXP2-8E-5TN144I
Manufacturer Part Number
LFXP2-8E-5TN144I
Description
FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5TN144I
Number Of Macrocells
8000
Number Of Programmable I/os
100
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
226304
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
OSC Usage with VHDL - Example
COMPONENT OSCE
END COMPONENT;
begin
OSCInst0: OSCE
OSC Usage with Verilog - Example
module OSC_TOP(OSC_CLK);
output OSC_CLK;
OSCE OSCinst0 (.OSC(OSC_CLK));
endmodule
Setting Clock Preferences
Designers can use clock preferences to implement clocks to the desired performance. Preferences can be set in
the Pre-Map Preference Editor (Design Planner) or in preference files. Frequently used preferences are described
in Appendix C.
Power Supplies
Each PLL has its own power supply pin, VCCPLL. Since VCCAUX and VCCPLL are normally the same 3.3V, it is
recommended that they are driven from the same power supply on the circuit board, thus minimizing leakage. In
addition, each of these supplies should be independently isolated from the main 3.3V supply on the board using
proper board filtering techniques to minimize the noise coupling between them.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet:
Revision History
February 2007
February 2010
PORT (OSC:OUT
PORT MAP ( OSC=>
+1-503-268-8001 (Outside North America)
techsupport@latticesemi.com
www.latticesemi.com
Date
std_logic);
osc_int);
Version
01.0
01.1
Initial release.
Reconciled LOCK description among MachXO, LatticeXP2,
LatticeECP2/M and LatticeECP3.
9-23
Change Summary
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
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