LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 177

• Manufacturer Part Number: LFXP2-8E-5TN144I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5TN144I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-27. FIFO with Output Registers, Start of Data Read Cycle
Figure 10-28. FIFO with Output Registers, End of Data Read Cycle
And finally, if you select the option enable output register with RdEn, it still delays the data out by one clock cycle
(as compared to the non-pipelined FIFO). The RdEn should also be high during that clock cycle, otherwise the data
takes an extra clock cycle when the RdEn goes true.
Almost Full
Almost Full
Almost
Almost
Empty
Empty
Empty
Empty
Reset
Clock
WrEn
RdEn
Reset
Clock
WrEn
RdEn
Data
Data
Full
Full
Q
Q
Data_N-5
Invalid Data
Data_N-4
Data_N-3
Data_1
10-27
Invalid Data
Invalid Data
Data_N-2
Data_2
LatticeXP2 Memory Usage Guide
Data_N-1
Data_3
Data_4
Data_N