A54SX08A-TQG100 Actel, A54SX08A-TQG100 Datasheet - Page 105

FPGA - Field Programmable Gate Array 12K System Gates

A54SX08A-TQG100

Manufacturer Part Number
A54SX08A-TQG100
Description
FPGA - Field Programmable Gate Array 12K System Gates
Manufacturer
Actel
Datasheet

Specifications of A54SX08A-TQG100

Processor Series
A54SX08
Core
IP Core
Number Of Macrocells
512
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
130
Delay Time
4 ns to 8.4 ns
Supply Voltage (max)
5.25 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
2.25 V
Number Of Gates
8000
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A54SX08A-TQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A54SX08A-TQG100
Manufacturer:
MICROSEMI/美高森美
Quantity:
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Part Number:
A54SX08A-TQG100A
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A54SX08A-TQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version Changes in Current Version (v5 . 3)
February 2005
(June 2006)
v5.2
v5.1
v5.0
v4.0
–3 speed grades have been discontinued.
The
RoHS information was added to the
The
Revised
A54SX08A device.
The
The
The
The
The
"SX-A Family Architecture"
"Clock Resources"
"User Security"
"Power-Up/Down and Hot Swapping"
"Dedicated Mode"
Table 1-5
"JTAG Instructions"
"Design Considerations"
The
"Design Environment"
"Pin Description"
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
"Power Dissipation"
Table 2-11
"SX-A Timing Model"
"Programming" section
"Thermal Characteristics" section
"176-Pin TQFP"
"484-Pin FBGA"
"Temperature Grade Offering"
"Speed Grade and Temperature Grade Matrix"
"Programming"
Table 1
is new.
was updated.
was updated.
is new.
is new.
was updated.
was updated.
was updated.
was updated.
and the timing data to reflect the phase out of the –3 speed grade for the
was updated.
was updated.
is new
is new
was updated to add pins 81 to 90.
section is new.
is new.
was updated to add pins R4 to Y26
was updated.
was updated.
was updated with –2 data.
was updated.
was updated.
is new.
"Ordering
was updated.
was updated.
v5.3
Information".
is new.
SX-A Family FPGAs
Page
2-14
1-13
2-11
3-11
3-26
1-10
1-12
1-13
1-13
1-15
N/A
1-iii
1-iii
1-1
1-5
1-7
1-7
1-9
1-9
2-1
2-1
2-1
2-1
2-2
2-2
2-8
2-9
ii
i
4-1

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