A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 56

FPGA - Field Programmable Gate Array 500K System Gates

A2F500M3G-FGG484

Manufacturer Part Number
A2F500M3G-FGG484
Description
FPGA - Field Programmable Gate Array 500K System Gates
Manufacturer
Actel
Datasheet

Specifications of A2F500M3G-FGG484

Processor Series
A2F500
Core
ARM Cortex M3
Number Of Logic Blocks
24
Maximum Operating Frequency
100 MHz
Number Of Programmable I/os
204
Data Ram Size
64 KB
Delay Time
50 ns
Supply Voltage (max)
3.6 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
500000
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A2F500M3G-FGG484
Manufacturer:
ACTEL
Quantity:
6 800
Part Number:
A2F500M3G-FGG484
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A2F500M3G-FGG484
Quantity:
140
Part Number:
A2F500M3G-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A2F500M3G-FGG484I
Manufacturer:
ACTEL/爱特
Quantity:
20 000
SmartFusion DC and Switching Characteristics
Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
2- 44
Enable
Preset
Data
CLK
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
C
A
B
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive-Edge Triggered
D
E
DFN1E1P1
PRE
D
Q
E
Y
R e visio n 6
Array
Core
Data_out
G
H
K
F
J
I
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered
D
E
D
E
DFN1E1P1
DFN1E1P1
PRE
PRE
L
Q
Q
DOUT
EOUT

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