A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 16

• Manufacturer Part Number: A2F500M3G-FGG484
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG484

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 204
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
Table 2-4 • FPGA and Embedded Flash Programming, Storage and Operating Limits
Table 2-5 • Overshoot and Undershoot Limits
2 - 4
Product Grade
Commercial
Industrial
VCCxxxxIOBx
2.7 V or less
3 V
3.3 V
3.6 V
Notes:
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
3. This table does not provide PCI overshoot/undershoot limits.
maximum overshoot/undershoot has to be reduced by 0.15 V.
Power Supply Sequencing Requirement
SmartFusion devices have an on-chip 1.5 V regulator, but usage of an external 1.5 V supply is also
allowed while the on-chip regulator is disabled. In that case, the 3.3 V supplies (VCC33A, etc.) should be
powered before 1.5 V (VCC, etc.) supplies. The 1.5 V supplies should be enabled only after 3.3 V
supplies reach a value higher than 2.7 V.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every SmartFusion
circuits ensure easy transition from the powered-off state to the powered-up state of the device. The
many different supplies can power up in any sequence with minimized current spikes or surges. In
addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in
Figure 2-1 on page
There are five regions to consider during power-up.
SmartFusion I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCxxxxIOBx are above the minimum specified trip points
2. VCCxxxxIOBx > VCC – 0.75 V (typical)
Storage Temperature
Min. T
Min. T
Average VCCxxxxIOBx–GND Overshoot or Undershoot
Min. T
Min. T
J
J
J
J
Duration as a Percentage of Clock Cycle
= –40°C
= 100°C
= 85°C
= 0°C
2-6.
FPGA/FlashROM
FPGA/FlashROM
Embedded Flash
Embedded Flash
1
10%
10%
10%
10%
Element
5%
5%
5%
5%
R e vi s i o n 6
Grade Programming
2
< 10,000
< 15,000
< 10,000
< 15,000
< 1,000
< 1,000
Cycles
500
500
(Figure 2-1 on page
Maximum Overshoot/
Undershoot
1.49 V
1.19 V
0.88 V
0.54 V
0.79 V
0.45 V
1.4 V
1.1 V
®
Retention
20 years
20 years
10 years
20 years
20 years
10 years
5 years
5 years
device. These
2
2-6).