A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 100

• Manufacturer Part Number: A2F500M3G-FGG484
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG484

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 204
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
Inter-Integrated Circuit (I
Table 2-99 • I
2- 88
Parameter
V
V
V
I
I
V
T
T
Cin
R
R
D
t
t
t
t
t
t
Notes:
1. These maximum values are provided for information only. Minimum output buffer resistance values depend on
2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer
3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I
IL
IH
LOW
HIGH
HD;STA
SU;STA
HD;DAT
SU;DAT
FALL
RISE
IL
IH
OL
hyst
pull-up
pull-down
max
VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output
buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at
http://www.actel.com/download/ibis/default.aspx.
resistances,
http://www.actel.com/download/ibis/default.aspx.
Microcontroller Subsystem User’s
Commercial Case Conditions: T
Minimum input low voltage
Maximum input low voltage
Minimum input high voltage
Maximum input high voltage
Maximum output voltage low
Input current high
Input current low
Hysteresis of Schmitt trigger
inputs
Fall time
Rise time
Pin capacitance
Output buffer maximum pull-
down Resistance
Output buffer maximum pull-up
Resistance
Maximum data rate
Low period of I2C_x_SCL
High period of I2C_x_SCL
START hold time
START setup time
DATA hold time
DATA setup time
This section describes the DC and switching of the I
characteristics given are for a 100 pF load on the pins. For timing parameter definitions, refer to
47 on page
2
C Characteristics
use
2
2
the
Definition
1
2-89.
corresponding
3
3
3
1
3
Guide.
3
3
IBIS
J
2
= 85ºC, V
C) Characteristics
VIHmin to VILMax, C
VIHmin to VILMax, C
VILMax to VIHmin, C
VILMax to VIHmin, C
models
VIN = 0, f = 1.0 MHz
DD
R e visio n 6
I
Condition
Fast mode
located
= 1.425 V, –1 Speed Grade
OL
= 8 mA
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
C interface. Unless otherwise noted, all output
load
load
on
load
load
= 400 pF
= 100 pF
= 400pF
= 100pF
2
the
C) Peripherals section in the
SoC
SeeTable 2-35 on
See
See
See
page 2-30
See
See
See
Products
See
on page 2-29
Table 2-35
Table 2-35
Table 2-35
Table 2-35
Table 2-35
Table 2-35
Table 2-32
Value
15.0
19.5
400
150
4.0
5.2
8.0
50
1
1
1
1
1
1
Group
SmartFusion
website
pclk cycles
pclk cycles
pclk cycles
pclk cycles
pclk cycles
pclk cycles
Figure 2-
Kbps
Unit
pF
ns
ns
ns
ns
Ω
Ω
V
–
–
–
–
–
–
–
at