PCA9501D,118 NXP Semiconductors, PCA9501D,118 Datasheet - Page 12

• Manufacturer Part Number: PCA9501D,118
• Description: I/O Expanders, Repeaters & Hubs 8BIT I2C FMQB GPIONT PU2K EPR
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of PCA9501D,118

• Logic Family: PCA9501
• Number Of Lines (input / Output): 8.0 / 8.0
• Operating Supply Voltage: 2.5 V to 3.6 V
• Power Dissipation: 400 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 8.0
• Output Current: 25 mA
• Output Voltage: 5 V
• Package / Case: SO-20
• Mounting Type: Surface Mount
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Interface: I²C, SMBus
• Number Of I /o: 8
• Frequency - Clock: 400kHz
• Interrupt Output: Yes
• Includes: EEPROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935272364118 PCA9501D-T

NXP Semiconductors
PCA9501_4
Product data sheet
Fig 19. System configuration
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 20. Acknowledgement on the I
RECEIVER
SLAVE
SCL from master
by transmitter
data output
by receiver
data output
Rev. 04 — 10 February 2009
8-bit I
TRANSMITTER/
RECEIVER
condition
START
SLAVE
S
2
C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
2
C-bus
TRANSMITTER
1
MASTER
2
TRANSMITTER/
RECEIVER
MASTER
acknowledgement
not acknowledge
SLAVE
clock pulse for
acknowledge
8
MULTIPLEXER
PCA9501
© NXP B.V. 2009. All rights reserved.
002aaa987
I
2
9
C-BUS
002aaa966
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