WM8351GEB/V Wolfson Microelectronics, WM8351GEB/V Datasheet - Page 48

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WM8351GEB/V

Manufacturer Part Number
WM8351GEB/V
Description
Audio CODECs Audio CODEC plus pwr management
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8351GEB/V

Number Of Adc Inputs
2
Number Of Dac Outputs
2
Conversion Rate
48 KSPS
Interface Type
Serial (2-Wire, 3-Wire, 4-Wire)
Resolution
12 bit
Operating Supply Voltage
3.7 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
BGA
Minimum Operating Temperature
- 25 C
Number Of Channels
2 ADC/2 DAC
Supply Current
260 uA
Thd Plus Noise
- 83 dB
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
8
No. Of Output Channels
6
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
95dB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
WM8351
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When the GPIO5 pin is configured as CODEC_OPCLK, a clock derived from SYSCLK may be output
on this pin to provide clocking for other parts of the system. The frequency of this signal is set by
OPCLK_DIV.
Alternate GPIO pins can be used to provide ADCLRCLK and ADCBCLK as described in Section 20.
An inverted L/R clock signal ADCLRCLKB can also be generated. When this feature is used, the
LRCLK and BCLK pins support the DAC only, and the alternate GPIO pins support the ADC only.
Limited capability can be provided to support mixed sample rates by this method. (The selection of
USB mode and the supported values of the various SYSCLK dividers impose restrictions on what
combinations of clocking and sample rates may be configured.)
A slow clock derived from SYSCLK may be used to provide de-bouncing of the headphone detect
function, and to set the timeout period for volume updates when zero-cross functions are used. This
clock is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.
The overall CODEC clocking scheme is illustrated in Figure 35.
Figure 35 Audio CODEC Clocking
PD, March 2010, Rev 4.2
Production Data
48

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