DS92LV2411SQ/NOPB National Semiconductor, DS92LV2411SQ/NOPB Datasheet - Page 9

• Manufacturer Part Number: DS92LV2411SQ/NOPB
• Description: IC SERIALIZER 24BIT 48LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV2411SQ/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Name
Control and Configuration
PDB
ID[x]
SCL
SDA
BISTEN
RES
NC
Channel-Link II — CML Serial Interface
RIN+
RIN-
CMF
ROUT+
ROUT-
Power and Ground
Power must be supplied to all power pins for normal operation
VDDL
VDDIR
VDDR
VDDSC
VDDPR
VDDCMLO
VDDIO
GND
NOTE: 1 = HIGH, 0 = LOW
The VDD (V
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
DDn
30, 31, 45,
13, 24, 38
1, 15, 16,
and V
46, 60
43, 55
Pin #
4, 58
DAP
59
56
44
47
49
50
51
52
53
29
48
57
54
3
2
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
w/ pull-down
w/ pull-down
w/ pull-down
I, LVCMOS
I, LVCMOS
Open Drain
Open Drain
I, LVCMOS
I, LVCMOS
I/O, Type
LVCMOS
I, Analog
I, Analog
O, CML
O, CML
Ground
I, CML
I, CML
Power
Power
Power
Power
Power
Power
Power
I/O,
Description
Power Down Mode Input
PDB = 1, Des is enabled (normal operation).
Refer to “Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by
8. Control Registers are RESET.
I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See
I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to 3.3V.
I2C Serial Control Bus Data Input / Output - Optional
SDA requires an external pull-up resistor to 3.3V.
BIST Enable Input — Optional
BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
Reserved - tie LOW
Not Connected
Leave pin open (float)
True Input. The input must be AC Coupled with a 0.1 μF capacitor.
Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.
Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
True Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
Inverting Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
Logic Power, 1.8 V ±5%
Input Power, 1.8 V ±5%
RX High Speed Logic Power, 1.8 V ±5%
SSCG Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
RX High Speed Logic Power, 1.8 V ±5%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (V
DAP is the large metal contact at the bottom side, located at the center of the LLP package.
Connected to the ground plane (GND) with at least 9 vias.
9
DDIO
)
Table
11).
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Table