DS92LV2411SQ/NOPB National Semiconductor, DS92LV2411SQ/NOPB Datasheet - Page 5

• Manufacturer Part Number: DS92LV2411SQ/NOPB
• Description: IC SERIALIZER 24BIT 48LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV2411SQ/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Name
CONFIG
[1:0]
ID[x]
SCL
SDA
BISTEN
RES[2:0]
Channel-Link II — CML Serial Interface
DOUT+
DOUT-
Power and Ground
VDDL
VDDP
VDDHS
VDDTX
VDDIO
GND
NOTE: 1 = HIGH, 0 = LOW
The VDD (V
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
DDn
18, 16, 15
13, 12
Pin #
DAP
and V
31
20
19
14
17
22
30
6
8
9
7
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
I/O, LVCMOS
w/ pull-down
w/ pull-down
w/ pull-down
I, LVCMOS
I, LVCMOS
Open Drain
Open Drain
I, LVCMOS
I, LVCMOS
I/O, Type
I, Analog
O, CML
O, CML
Ground
Power
Power
Power
Power
Power
Description
00: Control Signal Filter DISABLED. Interfaces with DS92LV2412 or DS92LV0412
01: Control Signal Filter ENABLED. Interfaces with DS92LV2412 or DS92LV0412
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q
11: Reverse compatibility mode to interface with the DS90C124
I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See
I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to 3.3V.
I2C Serial Control Bus Data Input / Output - Optional
SDA requires an external pull-up resistor 3.3V.
BIST Mode — Optional
BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
Reserved - tie LOW
Non–Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
Logic Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
TX High Speed Logic Power, 1.8 V ±5%
Output Driver Power, 1.8 V ±5%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
5
Table
11.
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