DS92LV2411SQ/NOPB National Semiconductor, DS92LV2411SQ/NOPB Datasheet - Page 4

• Manufacturer Part Number: DS92LV2411SQ/NOPB
• Description: IC SERIALIZER 24BIT 48LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV2411SQ/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Pin Name
LVCMOS Parallel Interface
DI[7:0]
DI[15:8]
DI[23:16]
CI1
CI2
CI3
CLKIN
Control and Configuration
PDB
VODSEL
De-Emph
RFB
DS92LV2411 Serializer Pin Descriptions
34, 33, 32, 29,
42, 41, 40, 39,
28, 27, 26, 25
38, 37, 36, 35
46, 45, 44, 43
2, 1, 48, 47,
Pin #
10
21
24
23
11
5
3
4
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I/O, Type
w/ pull-up
I, Analog
Description
Parallel Interface Data Input Pins
For 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB.
Parallel Interface Data Input Pins
For 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB.
Parallel Interface Data Input Pins
For 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB.
Control Signal Input
For Display/Video Application:
CI1 = Data Enable Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum
transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
Control Signal Input
For Display/Video Application:
CI2 = Horizontal Sync Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum
transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
Control Signal Input
For Display/Video Application:
CI3 = Vertical Sync Input
CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed
is 130 clock cycle wide.
Clock Input
Latch/data strobe edge set by RFB pin.
Power-down Mode Input
PDB = 1, Ser is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Ser is powered down
When the Ser is in the power-down state, the driver outputs (DOUT+/-) are both logic high,
the PLL is shutdown, IDD is minimized. Control Registers are RESET.
Differential Driver Output Voltage Select
VODSEL = 1, CML VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph applications
VODSEL = 0, CML VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low
power mode.
This is can also be control by I2C register.
De-Emphasis Control
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See
This can also be controlled by I2C register access.
Clock Input Latch/Data Strobe Edge Select
RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
This can also be controlled by I2C register access.
Table
4.
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