S9S08DN32F1MLC Freescale Semiconductor, S9S08DN32F1MLC Datasheet - Page 344

• Manufacturer Part Number: S9S08DN32F1MLC
• Description: IC MCU 8BIT 32KB FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08DN32F1MLC

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Processor Series: S08D
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 26
• Operating Supply Voltage: 3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Appendix B Timer Pulse-Width Modulator (TPMV2)
at the transition from the value set in the modulus register and the next lower count value. This corresponds
to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.)
B.4.3
The meaning of channel interrupts depends on the current mode of the channel (input capture, output
compare, edge-aligned PWM, or center-aligned PWM).
When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising
edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the
selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in
Section B.4.1, “Clearing Timer Interrupt
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step
sequence described in
B.4.4
For channels that are configured for PWM operation, there are two possibilities:
The flag is cleared by the 2-step sequence described in
344
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•
When the channel is configured for edge-aligned PWM, the channel flag is set when the timer
counter matches the channel value register that marks the end of the active duty cycle period.
When the channel is configured for center-aligned PWM, the timer count matches the channel
value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start
and at the end of the active duty cycle, which are the times when the timer counter matches the
channel value register.
Channel Event Interrupt Description
PWM End-of-Duty-Cycle Events
Section B.4.1, “Clearing Timer Interrupt
MC9S08DN60 Series Data Sheet, Rev 3
Flags.”
Section B.4.1, “Clearing Timer Interrupt
Flags.”
Freescale Semiconductor
Flags.”