AT91SAM7SE512B-AU Atmel, AT91SAM7SE512B-AU Datasheet - Page 67
AT91SAM7SE512B-AU
Manufacturer Part Number
AT91SAM7SE512B-AU
Description
IC ARM7 MCU FLASH 512K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE512B-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Core
ARM7TDMI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7SE512B-AU
Manufacturer:
TOREX
Quantity:
15 600
Part Number:
AT91SAM7SE512B-AU
Manufacturer:
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Quantity:
20 000
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14. Real-time Timer (RTT)
14.1
14.2
Figure 14-1. Real-time Timer
14.3
6222F–ATARM–14-Jan-11
SLCK
RTT_MR
Overview
Block Diagram
Functional Description
RTTRST
reload
Divider
16-bit
RTT_MR
RTPRES
The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen-
erates a periodic interrupt or/and triggers an alarm on a programmed value.
The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by
Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field
RTPRES of the Real-time Mode Register (RTT_MR).
Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz
signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 2
sponding to more than 136 years, then roll over to 0.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best
accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but
may result in losing status events because the status register is cleared two Slow Clock cycles
after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow
Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the
interrupt must be disabled in the interrupt handler and re-enabled when the status register is
clear.
RTT_VR
RTT_AR
RTT_MR
RTTRST
0
1
Counter
CRTV
32-bit
ALMV
0
SAM7SE512/256/32 Preliminary
RTT_SR
RTT_SR
RTT_SR
=
read
reset
reset
set
set
RTTINC
ALMS
RTTINCIEN
RTT_MR
RTT_MR
ALMIEN
rtt_alarm
32
seconds, corre-
rtt_int
67
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