ATMEGA48PA-MNR Atmel, ATMEGA48PA-MNR Datasheet - Page 178
![MCU AVR 4KB FLASH 20MHZ 28QFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATMEGA48PA-MNR
Manufacturer Part Number
ATMEGA48PA-MNR
Description
MCU AVR 4KB FLASH 20MHZ 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA48PA-AN.pdf
(448 pages)
Specifications of ATMEGA48PA-MNR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, UART, I2C
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA48A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.3.1
8161D–AVR–10/09
Internal Clock Generation – The Baud Rate Generator
Figure 19-2
Figure 19-2. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
osc
), is loaded with the UBRRn value each time the counter has counted down to zero or when
txclk
rxclk
xcki
xcko
fosc
DDR_XCKn
XCKn
Pin
shows a block diagram of the clock generation logic.
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
xcko
xcki
OSC
Down-Counter
Prescaling
Register
UBRRn
Sync
ATmega48PA/88PA/168PA/328P
UBRRn+1
foscn
Detector
UCPOLn
Edge
/2
Figure
osc
/(UBRRn+1)). The Transmitter divides the
/4
19-2.
/2
DDR_XCKn
U2Xn
0
1
0
1
0
1
1
0
UMSELn
txclk
rxclk
178
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