ATMEGA48PA-MNR Atmel, ATMEGA48PA-MNR Datasheet - Page 174
![MCU AVR 4KB FLASH 20MHZ 28QFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATMEGA48PA-MNR
Manufacturer Part Number
ATMEGA48PA-MNR
Description
MCU AVR 4KB FLASH 20MHZ 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA48PA-AN.pdf
(448 pages)
Specifications of ATMEGA48PA-MNR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, UART, I2C
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA48A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 174 of 448
- Download datasheet (13Mb)
18.5.2
8161D–AVR–10/09
SPSR – SPI Status Register
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 18-5.
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega48PA/88PA/168PA/328P and will always read as
zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f
or lower.
The SPI interface on the ATmega48PA/88PA/168PA/328P is also used for program memory
and EEPROM downloading or uploading. See
Bit
0x2D (0x4D)
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
Relationship Between SCK and the Oscillator Frequency
SPIF
R
7
0
Table
WCOL
SPR1
R
6
0
0
0
1
1
0
0
1
1
18-5). This means that the minimum SCK period will be two CPU
ATmega48PA/88PA/168PA/328P
R
5
–
0
SPR0
R
4
–
0
0
1
0
1
0
1
0
1
page 308
R
3
–
0
for serial programming and verification.
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
R
2
–
0
R
1
–
0
SPI2X
R/W
0
0
SPSR
osc
osc
174
/4
is
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