PIC18F86J72-I/PT Microchip Technology, PIC18F86J72-I/PT Datasheet - Page 468

• Manufacturer Part Number: PIC18F86J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 12MIPS
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
Extended Instruction Set
External Oscillator Modes
F
Fail-Safe Clock Monitor............................................. 319, 329
Fast Register Stack............................................................. 59
Firmware Instructions........................................................ 333
Flash Configuration Words................................................ 319
Flash Program Memory....................................................... 77
FSCM. See Fail-Safe Clock Monitor.
G
GOTO................................................................................ 355
DS39979A-page 468
Baud Rate Generator (BRG)..................................... 243
Synchronous Master Mode ....................................... 254
Synchronous Slave Mode ......................................... 257
ADDFSR ................................................................... 377
ADDULNK ................................................................. 377
CALLW...................................................................... 378
MOVSF ..................................................................... 378
MOVSS ..................................................................... 379
PUSHL ...................................................................... 379
SUBFSR ................................................................... 380
SUBULNK ................................................................. 380
Clock Input (EC and ECPLL Modes) .......................... 30
HS ............................................................................... 29
Exiting Fail-Safe Operation ....................................... 330
Interrupts in Power-Managed Modes ........................ 330
POR or Wake-up From Sleep ................................... 330
WDT During Oscillator Failure .................................. 329
Associated Registers .................................................. 86
Control Registers ........................................................ 78
Erase Sequence ......................................................... 82
Erasing ........................................................................ 82
Operation During Code-Protect .................................. 86
Reading....................................................................... 81
Table Pointer
Table Pointer Boundaries ........................................... 80
Table Reads and Table Writes ................................... 77
Write Sequence .......................................................... 83
Write Sequence (Word Programming) ........................ 85
Writing ......................................................................... 83
Auto-Baud Rate Detect ..................................... 246
Baud Rate Error, Calculating ............................ 243
Baud Rates, Associated Registers ................... 243
Baud Rates, Asynchronous Modes................... 244
High Baud Rate Select (BRGH Bit)................... 243
Operation in Power-Managed Modes ............... 243
Sampling ........................................................... 243
Associated Registers, Receive ......................... 256
Associated Registers, Transmit ........................ 255
Reception.......................................................... 256
Transmission..................................................... 254
Associated Registers, Receive ......................... 258
Associated Registers, Transmit ........................ 257
Reception.......................................................... 258
Transmission..................................................... 257
EECON1 and EECON2 ...................................... 78
TABLAT (Table Latch) Register.......................... 80
TBLPTR (Table Pointer) Register ....................... 80
Boundaries Based on Operation......................... 80
Unexpected Termination..................................... 86
Write Verify ......................................................... 86
Preliminary
H
Hardware Multiplier............................................................. 87
I
I/O Ports............................................................................ 105
I
INCF ................................................................................. 355
INCFSZ............................................................................. 356
In-Circuit Debugger........................................................... 331
In-Circuit Serial Programming (ICSP)....................... 319, 331
Indexed Literal Offset Addressing
Indexed Literal Offset Mode.............................................. 381
Indirect Addressing ............................................................. 72
INFSNZ............................................................................. 356
Initialization Conditions for all Registers ....................... 49–54
Instruction Cycle ................................................................. 60
2
C Mode (MSSP) ............................................................. 204
8 x 8 Multiplication Algorithms .................................... 87
Operation .................................................................... 87
Performance Comparison (table)................................ 87
Input Voltage Considerations.................................... 105
Open-Drain Outputs.................................................. 106
Output Pin Drive ....................................................... 105
Pin Capabilities ......................................................... 105
Pull-up Configuration ................................................ 106
Acknowledge Sequence Timing ............................... 232
Associated Registers ................................................ 238
Baud Rate Generator ............................................... 225
Bus Collision
Clock Arbitration ....................................................... 226
Clock Stretching........................................................ 218
Clock Synchronization and the CKP Bit.................... 219
Effects of a Reset ..................................................... 233
General Call Address Support .................................. 222
I
Master Mode............................................................. 223
Multi-Master Communication, Bus Collision
Multi-Master Mode .................................................... 233
Operation .................................................................. 209
Read/Write Bit Information (R/W Bit) ................ 209, 211
Registers .................................................................. 204
Serial Clock (SCK/SCL)............................................ 211
Slave Mode............................................................... 209
Sleep Operation........................................................ 233
Stop Condition Timing .............................................. 232
and Standard PIC18 Instructions.............................. 381
Clocking Scheme........................................................ 60
Flow/Pipelining............................................................ 60
2
C Clock Rate w/BRG.............................................. 225
During a Repeated Start Condition................... 236
During a Stop Condition ................................... 237
10-Bit Slave Receive Mode (SEN = 1) ............. 218
10-Bit Slave Transmit Mode ............................. 218
7-Bit Slave Receive Mode (SEN = 1) ............... 218
7-Bit Slave Transmit Mode ............................... 218
Baud Rate Generator ....................................... 225
Operation.......................................................... 224
Reception ......................................................... 229
Repeated Start Condition Timing ..................... 228
Start Condition Timing ...................................... 227
Transmission .................................................... 229
and Arbitration .................................................. 233
Address Masking .............................................. 210
Addressing........................................................ 209
Reception ......................................................... 211
Transmission .................................................... 211
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