CLRC63201T/0FE,112 NXP Semiconductors, CLRC63201T/0FE,112 Datasheet - Page 96

• Manufacturer Part Number: CLRC63201T/0FE,112
• Description: IC I.CODE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: I-Coder

Specifications of CLRC63201T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693, ISO18000-3
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2199-5; 935269690112; CLRC632; CLRC63201TD

NXP Semiconductors
CLRC632_35
Product data sheet
PUBLIC
11.5.1.2 Relevant LoadConfig command error flags
11.5.2.1 CRC coprocessor settings
11.5.2.2 CRC coprocessor status flags
11.5.2 CalcCRC command 12h
Valid EEPROM starting byte addresses are between 10h and 60h.
Copying from block 8h to 1Fh (keys) is restricted. Reading from these addresses sets the
flag AccessErr = logic 1.
Addresses above 1FFh are taken as modulo 200h; see
EEPROM memory organization.
Table 152. CalcCRC command 12h
The CalcCRC command takes all the data from the FIFO buffer as the input bytes for the
CRC coprocessor. All data stored in the FIFO buffer before the command is started is
processed.
This command does not return any data to the FIFO buffer but the content of the CRC can
be read using the CRCResultLSB and CRCResultMSB registers.
The CalcCRC command can only be started by the microprocessor and it does not
automatically stop. It must be stopped by the microprocessor sending the Idle command.
If the FIFO buffer is empty, the CalcCRC command waits for further input before
proceeding.
Table 153
Table 153. CRC coprocessor parameters
The CRC polynomial for the 8-bit CRC is fixed to x
The CRC polynomial for the 16-bit CRC is fixed to x
The CRCReady status flag indicates that the CRC coprocessor has finished processing
all the data bytes in the FIFO buffer. When the CRCReady flag is set to logic 1, an
interrupt is requested which sets the TxIRq flag. This supports interrupt driven use of the
CRC coprocessor.
When CRCReady and TxIRq flags are set to logic 1 the content of the CRCResultLSB
and CRCResultMSB registers and the CRCErr flag are valid. The CRCResultLSB and
CRCResultMSB registers hold the content of the CRC, the CRCErr flag indicates CRC
validity for the processed data.
Command Value Action
CalcCRC
Parameter
CRC register
length
CRC algorithm
CRC preset value any
shows the parameters that can be configured for the CRC coprocessor.
12h
Value
8-bit or 16-bit CRC
ISO/IEC 14443 A or ISO/IEC 3309 CRC3309
activates the CRC coprocessor
Rev. 3.5 — 10 November 2009
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
073935
8
16
Bit
CRC8
CRCPresetLSB CRCPresetLSB
CRCPresetMSB CRCPresetMSB
+ x
Arguments and
data
data byte stream
+ x
4
Section 9.2 on page 12
+ x
12
3
+ x
+ x
5
2
+ 1.
+ 1.
Register
ChannelRedundancy
ChannelRedundancy
CLRC632
© NXP B.V. 2009. All rights reserved.
Returned data
-
for the
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