CLRC63201T/0FE,112 NXP Semiconductors, CLRC63201T/0FE,112 Datasheet - Page 21

• Manufacturer Part Number: CLRC63201T/0FE,112
• Description: IC I.CODE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: I-Coder

Specifications of CLRC63201T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693, ISO18000-3
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2199-5; 935269690112; CLRC632; CLRC63201TD

NXP Semiconductors
Table 21.
CLRC632_35
Product data sheet
PUBLIC
Register
InterruptEn
InterruptRq
Interrupt control registers
9.4.2.1 Controlling interrupts and getting their status
9.4.1 Interrupt sources overview
9.4.2 Interrupt request handling
Bit 7
SetIEn
SetIRq
Table 20
interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set
when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one
to the TReLoadValue[7:0] with bit TAutoRestart enabled.
Bit TxIRq indicates interrupts from different sources and is set as follows:
The RxIRq flag bit indicates an interrupt when the end of the received data is detected.
The IdleIRq flag bit is set when a command finishes and the content of the Command
register changes to Idle.
When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page
logic 1.
When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page
logic 1.
Table 20.
The CLRC632 informs the microprocessor about the interrupt request source by setting
the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as
source for an interrupt can be masked by the InterruptEn register interrupt enable bits.
Interrupt flag
TimerIRq
TxIRq
RxIRq
IdleIRq
HiAlertIRq
LoAlertIRq
•
•
•
the transmitter automatically sets the bit TxIRq interrupt when it is active and its state
changes from sending data to transmitting the end of frame pattern
the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been
processed indicated by bit CRCReady = logic 1
when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit
E2Ready = logic 1
Bit 6
reserved
reserved
shows the integrated interrupt flags, related source and setting condition. The
Interrupt sources
Interrupt source
timer unit
transmitter
CRC coprocessor
EEPROM
receiver
Command register
FIFO buffer
FIFO buffer
Bit 5
TimerIEn
TimerIRq
Rev. 3.5 — 10 November 2009
20) and bit HiAlert = logic 1, then the HiAlertIRq flag bit is set to
20) and bit LoAlert = logic 1, then LoAlertIRq flag bit is set to
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
073935
Bit 4
TxIEn
TxIRq
Bit 3
RxIEn
RxIRq
Trigger action
timer counts from 1 to 0
a data stream, transmitted to the card, ends
all data from the FIFO buffer has been processed
all data from the FIFO buffer has been
programmed
a data stream, received from the card, ends
command execution finishes
FIFO buffer is full
FIFO buffer is empty
Bit 2
IdleIEn
IdleIRq
Bit 1
HiAlertIEn
HiAlertIRq
CLRC632
© NXP B.V. 2009. All rights reserved.
Bit 0
LoAlertIEn
LoAlertIRq
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