CLRC63201T/0FE,112 NXP Semiconductors, CLRC63201T/0FE,112 Datasheet - Page 45

• Manufacturer Part Number: CLRC63201T/0FE,112
• Description: IC I.CODE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: I-Coder

Specifications of CLRC63201T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693, ISO18000-3
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2199-5; 935269690112; CLRC632; CLRC63201TD

NXP Semiconductors
Table 39.
CLRC632_35
Product data sheet
PUBLIC
Sub
address
(Hex)
Page 0: Command and status
00h
01h
02h
03h
04h
05h
06h
07h
Page 1: Control and status
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Page 2: Transmitter and coder control
10h
11h
12h
13h
14h
15h
16h
17h
Page 3: Receiver and decoder control
18
19
1A
1B
1C
1D
1Eh
1Fh
Register name
Page
Command
FIFOData
PrimaryStatus
FIFOLength
SecondaryStatus
InterruptEn
InterruptRq
Page
Control
ErrorFlag
CollPos
TimerValue
CRCResultLSB
CRCResultMSB
BitFraming
Page
TxControl
CwConductance
ModConductance
CoderControl
ModWidth
ModWidthSOF
TypeBFraming
Page
RxControl1
DecoderControl
BitPhase
RxThreshold
BPSKDemControl
RxControl2
ClockQControl
CLRC632 register overview
10.3 Register overview
Function
selects the page register
starts and stops command execution
input and output of 64-byte FIFO buffer
receiver and transmitter and FIFO buffer status flags
number of bytes buffered in the FIFO buffer
secondary status flags
enable and disable interrupt request control bits
interrupt request flags
selects the page register
control flags for timer unit, power saving etc
show the error status of the last command executed
bit position of the first bit-collision detected on the RF interface
value of the timer
LSB of the CRC coprocessor register
MSB of the CRC coprocessor register
adjustments for bit oriented frames
selects the page register
controls the operation of the antenna driver pins TX1 and TX2
selects the conductance of the antenna driver pins TX1 and TX2
defines the driver output conductance
sets the clock frequency and the encoding
selects the modulation pulse width
selects the SOF pulse-width modulation (I-CODE1 fast mode)
defines the framing for ISO/IEC 14443 B communication
selects the page register
controls receiver behavior
controls decoder behavior
selects the bit-phase between transmitter and receiver clock
selects thresholds for the bit decoder
controls BPSK receiver behavior
controls decoder and defines the receiver input source
clock control for the 90 phase-shifted Q-channel clock
Rev. 3.5 — 10 November 2009
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
073935
Refer to
Table 41 on page 50
Table 43 on page 50
Table 45 on page 51
Table 47 on page 51
Table 49 on page 52
Table 51 on page 53
Table 53 on page 53
Table 55 on page 54
Table 41 on page 50
Table 57 on page 55
Table 59 on page 55
Table 61 on page 56
Table 63 on page 57
Table 65 on page 57
Table 67 on page 57
Table 69 on page 58
Table 41 on page 50
Table 71 on page 59
Table 73 on page 60
Table 75 on page 60
Table 77 on page 61
Table 79 on page 62
Table 81 on page 62
Table 83 on page 63
Table 41 on page 50
Table 85 on page 64
Table 87 on page 65
Table 89 on page 65
Table 91 on page 66
Table 93 on page 66
Table 95 on page 67
Table 97 on page 67
CLRC632
© NXP B.V. 2009. All rights reserved.
45 of 126