ATMEGA128RZAV-8MU Atmel, ATMEGA128RZAV-8MU Datasheet - Page 246
ATMEGA128RZAV-8MU
Manufacturer Part Number
ATMEGA128RZAV-8MU
Description
MCU ATMEGA1281/AT86RF230 64-QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA640V-8CU.pdf
(38 pages)
2.ATMEGA640V-8CU.pdf
(444 pages)
3.AT86RF230-ZU.pdf
(98 pages)
Specifications of ATMEGA128RZAV-8MU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-QFN
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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23.5
2549M–AVR–09/10
Overview of the TWI Module
Figure 23-8. Arbitration Between Two Masters
Note that arbitration is not allowed between:
•
•
•
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
The TWI module is comprised of several submodules, as shown in
registers drawn in a thick line are accessible through the AVR data bus.
A REPEATED START condition and a data bit.
A STOP condition and a data bit.
A REPEATED START and a STOP condition.
Synchronized
SCL Line
SDA from
SDA from
Master A
Master B
SDA Line
START
ATmega640/1280/1281/2560/2561
Arbitration, SDA
Master A Loses
Figure 23-9 on page
A
SDA
247. All
246
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