ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 55

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Watchdog Timer
Control Register –
WDTCR
2467V–AVR–02/11
Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON.
Figure 28. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega128 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit
must also be set when changing the prescaler bits.
Configuration of the Watchdog Timer” on page 57.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
Bit
Read/Write
Initial Value
M103C
Unprogrammed
Unprogrammed
Programmed
Programmed
R
7
–
0
WDTON
Unprogrammed
Unprogrammed
Programmed
Programmed
R
6
–
0
OSCILLATOR
WATCHDOG
R
5
–
0
Safety
Level
1
2
0
2
WDCE
R/W
4
0
WDT Initial
State
Disabled
Enabled
Disabled
Enabled
WDE
R/W
3
0
See “Timed Sequences for Changing the
WDP2
R/W
2
0
How to Disable
the WDT
Timed
sequence
Always enabled
Timed
sequence
Always enabled
WDP1
R/W
1
0
WDP0
R/W
ATmega128
0
0
How to
Change
Time-out
Timed
sequence
Timed
sequence
No
restriction
Timed
sequence
WDTCR
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