ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 148

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Force Output
Compare
Compare Match
Blocking by TCNT2
Write
Using the Output
Compare Unit
Compare Match
Output Unit
148
ATmega128
ering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register
to either top or bottom of the counting sequence. The synchronization prevents the occurrence
of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2 Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR2 buffer Register, and if double buffering is disabled
the CPU will access the OCR2 directly.
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by
writing a one to the force output compare (FOC2) bit. Forcing compare match will not set the
OCF2 flag or reload/clear the timer, but the OC2 pin will be updated as if a real compare match
had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled).
All CPU write operations to the TCNT2 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized
to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is
enabled.
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT2 when using the output compare channel,
independently of whether the Timer/Counter is running or not. If the value written to TCNT2
equals the OCR2 value, the compare match will be missed, resulting in incorrect waveform gen-
eration. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is
downcounting.
The setup of the OC2 should be performed before setting the Data Direction Register for the port
pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare
(FOC2) strobe bits in normal mode. The OC2 Register keeps its value even when changing
between waveform generation modes.
Be aware that the COM21:0 bits are not double buffered together with the compare value.
Changing the COM21:0 bits will take effect immediately.
The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses
the COM21:0 bits for defining the output compare (OC2) state at the next compare match. Also,
the COM21:0 bits control the OC2 pin output source.
the logic affected by the COM21:0 bit setting. The I/O registers, I/O bits, and I/O pins in the fig-
ure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT)
that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference
is for the internal OC2 Register, not the OC2 pin. If a System Reset occur, the OC2 Register is
reset to “0”.
Figure 64
shows a simplified schematic of
2467V–AVR–02/11