ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 63

IC AVR MCU 2.4GHZ XCEIVER 64QFN

ATMEGA128RFA1-ZU

Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr

Specifications of ATMEGA128RFA1-ZU

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Moving Interrupts
Between Application
and Boot Space
MCU Control Register
– MCUCR
2467V–AVR–02/11
The General Interrupt Control Register controls the placement of the interrupt vector table.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash
memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot
Loader section of the flash. The actual address of the start of the Boot Flash section is deter-
mined by the BOOTSZ fuses. Refer to the section
Self-Programming” on page 273
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:
Bit
Read/Write
Initial Value
$F049
$F04A
$F04B
If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If interrupt vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section
Write Self-Programming” on page 273
SRE
R/W
7
0
SRW10
out
sei
<instr>
R/W
6
0
SPL,r16
R/W
SE
5
0
xxx
for details. To avoid unintentional changes of interrupt vector
SM1
R/W
4
0
; Enable interrupts
for details on Boot Lock bits.
SM0
R/W
3
0
“Boot Loader Support – Read-While-Write
SM2
R/W
2
0
“Boot Loader Support – Read-While-
IVSEL
R/W
1
0
IVCE
R/W
ATmega128
0
0
MCUCR
63

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