SX1212IWLTRT Semtech, SX1212IWLTRT Datasheet - Page 39

• Manufacturer Part Number: SX1212IWLTRT
• Description: IC TXRX 300MHZ-510MHZ 32-TQFN
• Manufacturer: Semtech

Specifications of SX1212IWLTRT

• Frequency: 300MHz ~ 510MHz
• Data Rate - Maximum: 150kbps
• Modulation Or Protocol: FSK, OOK
• Applications: AMR, ISM, Home Automation, Process Control
• Power - Output: 12.5dBm
• Sensitivity: -110dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Modulation Type: FSK/OOK
• Package Type: TQFN EP
• Operating Supply Voltage (min): 2.1V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: SX1212IWLTR

All interrupt sources and flags are configured in the IRQParam section of the configuration register, with the
exception of Fifo_threshold :
Table 16 below summarizes the status of the FIFO when switching between different modes
Table 16: Status of FIFO when Switching Between Different Modes of the Chip
Rev 2 – June 18th, 2009
ADVANCED COMMUNICATIONS & SENSING
/Fifoempty: /Fifoempty interrupt source is low when byte 0, i.e. whole FIFO, is empty. Otherwise it is high.
Write_byte: Write_byte interrupt source goes high for 1 bit period each time a new byte is transferred from the
SR to the FIFO (i.e. each time a new byte is received)
Fifofull: Fifofull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.
Fifo_overrun_clr: Fifo_overrun_clr flag is set when a new byte is written by the user (in Tx or Standby modes)
or the SR (in Rx mode) while the FIFO is already full. In this case, data is lost and the flag should be cleared by
writing a 1. The bit can also be used anytime to clear FIFO and relaunch a new Rx or Tx process
Tx_done: Tx_done interrupt source goes high when FIFO is empty and the SR’s last bit has been send to the
modulator (i.e. the last bit of the packet has been sent). One bit period delay is required after the rising edge of
Tx_done to ensure correct RF transmission of the last bit. In practice this may not require special care in the uC
software due to IRQ processing time.
Fifo_threshold: Fifo_threshold interrupt source’s behavior can be programmed via MCParam_Fifo_thresh (B
value). This behavior is illustrated in Figure 32.
From
Stby
Stby
Rx
Rx
Tx
Tx
Any
5.2.3. Sync Word Recognition
5.2.2.3. Interrupt Sources and Flags
5.2.2.4. FIFO Clearing
To
Tx
Rx
Tx
Stby
Rx
Stby
Sleep
Cleared
Not cleared
Cleared
IRQ source
FIFO Status
Cleared
Not cleared
Cleared
Not cleared
Cleared
Figure 32: FIFO Threshold IRQ Source Behavior
1
0
Comments
In Buffered mode, FIFO cannot be written in Stby before Tx
In Packet mode, FIFO can be written in Stby before Tx
In Packet & Buffered modes FIFO can be read in Stby after Rx
Page 39 of 77
B
B+1
# of bytes in FIFO
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