SI4330-B1-FMR Silicon Laboratories Inc, SI4330-B1-FMR Datasheet - Page 5
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SI4330-B1-FMR
Manufacturer Part Number
SI4330-B1-FMR
Description
IC RX ISM 240-960MHZ 20VQFN
Manufacturer
Silicon Laboratories Inc
Specifications of SI4330-B1-FMR
Frequency
240MHz ~ 960MHz
Sensitivity
-121dBm
Data Rate - Maximum
256 kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
Remote Control, RKE, Security Systems
Current - Receiving
18.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Features
RSSI Equipped
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI4330-B1-FMR
Manufacturer:
HIROSE
Quantity:
3 200
Part Number:
SI4330-B1-FMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Si4330-B1
L
F
I S T OF
IGURES
Figure 1. RX Application Example............................................................................................ 14
Figure 2. SPI Timing.................................................................................................................. 16
Figure 3. SPI Timing—READ Mode ..........................................................................................17
Figure 4. SPI Timing—Burst Write Mode .................................................................................. 17
Figure 5. SPI Timing—Burst Read Mode .................................................................................. 17
Figure 6. State Machine Diagram.............................................................................................. 18
Figure 7. RX Timing .................................................................................................................. 22
Figure 8. Sensitivity at 1% PER vs. Carrier Frequency Offset .................................................. 26
Figure 9. PLL Synthesizer Block Diagram................................................................................. 30
Figure 10. FIFO Threshold ........................................................................................................32
Figure 11. Packet Structure....................................................................................................... 33
Figure 12. Required RX Packet Structure with Packet Handler Disabled ................................. 33
Figure 13. Multiple Packets in RX Packet Handler.................................................................... 34
Figure 14. Multiple Packets in RX with CRC or Header Error ................................................... 34
Figure 15. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 36
Figure 16. Manchester Coding Example ...................................................................................36
Figure 17. Header ..................................................................................................................... 38
Figure 18. POR Glitch Parameters............................................................................................ 40
Figure 19. General Purpose ADC Architecture ......................................................................... 42
Figure 20. Temperature Ranges using ADC8 ........................................................................... 44
Figure 21. WUT Interrupt and WUT Operation.......................................................................... 47
Figure 22. Low Duty Cycle Mode .............................................................................................. 48
Figure 23. RSSI Value vs. Input Power..................................................................................... 51
Figure 24. Receiver—Schematic Receiver—Top...................................................................... 52
Figure 25. 20-Pin Quad Flat No-Lead (QFN) ............................................................................60
Figure 26. PCB Land Pattern .................................................................................................... 61
Rev 1.0
5