SI4330-B1-FMR Silicon Laboratories Inc, SI4330-B1-FMR Datasheet - Page 30
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SI4330-B1-FMR
Manufacturer Part Number
SI4330-B1-FMR
Description
IC RX ISM 240-960MHZ 20VQFN
Manufacturer
Silicon Laboratories Inc
Specifications of SI4330-B1-FMR
Frequency
240MHz ~ 960MHz
Sensitivity
-121dBm
Data Rate - Maximum
256 kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
Remote Control, RKE, Security Systems
Current - Receiving
18.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Features
RSSI Equipped
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI4330-B1-FMR
Manufacturer:
HIROSE
Quantity:
3 200
Part Number:
SI4330-B1-FMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Si4330-B1
measurements for clear channel assessment (CCA), and carrier sense (CS) functionality.
Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital automatic
frequency control (AFC) in receive mode.
TM
A comprehensive programmable packet handler including key features of Silicon Labs’ EZMac
is integrated to
create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive
programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast,
group, and point-to-point communication.
A wireless communication channel can be corrupted by noise and interference, and it is therefore important to
know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of
erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted packet and
verified by the receiver to confirm that no errors have occurred. The packet handler and CRC can significantly
reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller.
5.6. Synthesizer
An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is provided
on-chip. Using a ΣΔ synthesizer has many advantages; it provides flexibility in choosing data rate, deviation,
channel frequency, and channel spacing.
The PLL and - modulator scheme is designed to support any desired frequency and channel spacing in the
range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band).
Selectable
Fref = 10 M
PFD
CP
LPF
RX
Divider
VCO
N
Figure 9. PLL Synthesizer Block Diagram
The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip
inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the
desired output frequency band. The modulus of the variable divide-by-N divider stage is controlled dynamically by
the output from the - modulator. The tuning resolution is sufficient to tune to the commanded frequency with a
maximum accuracy of 312.5 Hz anywhere in the range between 240–960 MHz.
5.6.1. VCO
The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and
fb[4:0] fields in "Register 75h. Frequency Band Select." In receive mode, the LO frequency is automatically shifted
downwards by the IF frequency of 937.5 kHz, allowing receive operation on the same frequency. The VCO
integrates the resonator inductor and tuning varactor, so no external VCO components are required.
The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank will
automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this might not
be desirable so the VCO calibration may be skipped by setting the appropriate register.
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Rev 1.0