AT24RF08-EK Atmel, AT24RF08-EK Datasheet - Page 11

• Manufacturer Part Number: AT24RF08-EK
• Description: KIT EVAL FOR AT24RF08CN-10SC
• Manufacturer: Atmel
• Type: Dual Access EEPROMr

Specifications of AT24RF08-EK

• Contents: Atmel Asset ID Kit CDROM, 4 RFID Tags, Reader with Serial Port Cable and 9V Power Supply
• For Use With/related Products: AT24RF08C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

State Transition Diagram
Error Detection
In order to increase the reliability of data transmissions to
the AT24RF08C, an error detection field must be sent by
the reader after the command word and each byte of data
sent from the reader. This field is computed as the number
of bits turned on in the byte modulo 4. In order to prevent
the checksum from matching the data for repeated 0’s or
1’s, the least significant bit (c
command word, only the 6 varying bits (b
compute the checksum.
There are several levels of error detection utilized to
prevent improper execution of a command. If the command
encoding is illegal, or the checksum is wrong, or if there is a
Manchester error in either the command or data or if there
Page/Word
Read
Global Reset Quiet
Page/Word
Write
SELECTED
3 bit listen
Progress
Write in
Write Done
Command/Data
0
Set Quiet
) is then inverted. For the
Window
Invalid
Ack
in
No Mod
7
Read Page/Word
- b
Write Page/Word
Wait for
no mod.
2
Set BL / PL
Set Tamper
All Globals
) are used to
INIT
Command/Data
Global Reset Quiet / Set Quiet
Mod Outside Ack Window
Invalid
Commands listed in italics
is a protection failure, then the entire command will be
aborted. Once in that state, the device will wait a random
period of time before transmitting the header sequence.
On both ID and data sent from the chip, the chip generates
and transmits a single parity bit after each 8 data bits are
sent to the reader. Internally, parity is computed in such a
way that the number of 1s in each 9 bit group is even. The
start and stop bits are not included in the parity generation.
No parity is generated on the 4-bit header. It is expected
that the reader may either embed additional error detection
bits within the data and/or read the data two or more times
to reduce the rate of bit errors.
Global
Reset
Quiet
SELECTED
Listen
Long
Global Reset Quiet
UNSELECTED
AT24RF08C
Set Quiet
QUIET
Set BL / PL
Set Tamper
All Globals
Global Write Word
Global Set Tamper
Other modulation ignored
Global Write Word
Global Set Tamper
Other modulation ignored
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