ATMEGA32M1-AU Atmel, ATMEGA32M1-AU Datasheet - Page 324
![MPU AVR 32K FLASH 20MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA32M1-AU
Manufacturer Part Number
ATMEGA32M1-AU
Description
MPU AVR 32K FLASH 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32M1-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32M1-AU
Manufacturer:
TYCO
Quantity:
210
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31. Instruction Set Summary
324
Mnemonics
FMULSU
MULSU
FMULS
CALL(*)
RCALL
JMP(*)
BREQ
BRCC
BRGE
BRHC
ADIW
MULS
FMUL
RJMP
ICALL
CPSE
SBRC
SBRS
BRBS
BRBC
BRNE
BRCS
BRSH
BRLO
BRPL
BRHS
BRTS
BRTC
BRVS
BRVC
SBIW
ANDI
BRMI
BRLT
SUBI
SBCI
EOR
COM
NEG
IJMP
RETI
SBIC
SBIS
ADD
ADC
SUB
SBC
AND
SBR
CBR
DEC
CLR
SER
MUL
RET
CPC
ORI
TST
INC
CPI
OR
CP
ATmega16M1/32M1/64M1
Operands
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rdl,K
Rd, K
Rd, K
Rdl,K
Rd, K
Rd, K
Rd,K
Rd,K
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
Rd
Rd
Rd
Rd
Rd
Rd
Rd
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
Fractional Multiply Signed with Unsigned
Subtract with Carry Constant from Reg.
Logical AND Register and Constant
Logical OR Register and Constant
Branch if Greater or Equal, Signed
Branch if Overflow Flag is Cleared
Compare Register with Immediate
Subtract with Carry two Registers
Branch if Less Than Zero, Signed
Skip if Bit in I/O Register Cleared
Branch if Half Carry Flag Cleared
Subtract Constant from Register
Subtract Immediate from Word
Skip if Bit in I/O Register is Set
Multiply Signed with Unsigned
Branch if Overflow Flag is Set
Skip if Bit in Register Cleared
Branch if Status Flag Cleared
Add with Carry two Registers
Fractional Multiply Unsigned
Branch if Half Carry Flag Set
Skip if Bit in Register is Set
Fractional Multiply Signed
Branch if Same or Higher
Branch if Status Flag Set
Branch if T Flag Cleared
Relative Subroutine Call
Add Immediate to Word
Exclusive OR Registers
Branch if Carry Cleared
Compare, Skip if Equal
Subtract two Registers
Logical AND Registers
Clear Bit(s) in Register
Test for Zero or Minus
Direct Subroutine Call
Logical OR Registers
Set Bit(s) in Register
Compare with Carry
Branch if T Flag Set
One’s Complement
Two’s Complement
Indirect Jump to (Z)
Branch if Not Equal
Branch if Carry Set
Add two Registers
Subroutine Return
Indirect Call to (Z)
Multiply Unsigned
Interrupt Return
Branch if Lower
Branch if Minus
Multiply Signed
Branch if Equal
Description
Clear Register
Relative Jump
Branch if Plus
Set Register
Direct Jump
Decrement
Increment
Compare
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if (Rd = Rr) PC ← PC + 2 or 3
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
Rdh:Rdl ← Rdh:Rdl + K
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • (0xFF - K)
Rd ← Rd + Rr + C
PC ← PC + k + 1
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
Rd ← Rd - Rr - C
PC ← PC + k + 1
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd - K - C
Rd ← Rd ⊕ Rd
Rd ← Rd ⊕ Rr
Rd ← Rd • Rd
Rd ← Rd + Rr
Rd ← Rd • Rr
Rd ← Rd v Rr
PC ← STACK
PC ← STACK
Rd ← Rd - Rr
Rd ← Rd • K
Rd ← Rd v K
Rd ← Rd v K
Rd ← Rd + 1
Rd ← Rd − 1
Operation
Rd ← Rd - K
Rd ← 0xFF
Rd − Rr − C
PC ← Z
PC ← Z
PC ← k
PC ← k
Rd − Rr
Rd − K
Z, C, N, V, H
Z, C, N, V, H
Z, C, N, V, S
Z, C, N, V, H
Z, C, N, V, H
Z, C, N, V, H
Z, C, N, V, H
Z, C, N, V, S
Z, C, N, V, H
Z, N, V, C, H
Z, N, V, C, H
Z, N, V, C, H
Z, C, N, V
Z, N, V
Z, N, V
Z, N, V
Z, N, V
Z, N, V
Z, N, V
Z, N, V
Z, N, V
Z, N, V
Z, N, V
Flags
Z, N, V
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z, C
Z, C
Z, C
Z, C
Z, C
Z, C
I
8209D–AVR–11/10
#Clocks
1/2/3
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
3
3
3
4
4
4
1
1
1
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