ATMEGA32M1-AU Atmel, ATMEGA32M1-AU Datasheet - Page 220
![MPU AVR 32K FLASH 20MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA32M1-AU
Manufacturer Part Number
ATMEGA32M1-AU
Description
MPU AVR 32K FLASH 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32M1-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32M1-AU
Manufacturer:
TYCO
Quantity:
210
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20.6.5
20.6.6
220
ATmega16M1/32M1/64M1
LINBTR – LIN Bit Timing Register
LINBRR – LIN Baud Rate Register
• Bit 1 - LCERR: Checksum Error Flag
• Bit 0 - LBERR: Bit Error Flag
• Bit 7 - LDISR: Disable Bit Timing Re synchronization
• Bits 5:0 - LBT[5:0]: LIN Bit Timing
• Bits 15:12 - Reserved Bits
• Bits 11:0 - LDIV[11:0]: Scaling of clk
Bit
Read/Write
Initial Value
Bit
Bit
Read/Write
Initial Value
written to zero when LINBRR is written.
UART baud rate.
– 0 = No error
– 1 = Checksum error
– 0 = no error
– 1 = Bit error
– 0 = Bit timing re-synchronization enabled (default)
– 1 = Bit timing re-synchronization disabled
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
Gives the number of samples of a bit.
Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63
These bits are reserved for future use. For compatibility with future devices, they must be
The LDIV value is used to scale the entering clk
LDISR
LDIV7
R/W
R/W
15
7
0
7
0
-
sample-time = (1/
LDIV6
R/W
14
R
6
0
6
0
-
-
R/(W)
LDIV5
LBT5
R/W
13
5
1
5
0
-
f
i/o
clk
R/(W)
LDIV4
LBT4
R/W
Frequency
12
4
0
i/o
4
0
-
) × (LDIV[11..0] + 1)
R/(W)
LDIV11
LBT3
LDIV3
R/W
3
0
11
3
0
i/o
frequency to achieve appropriate LIN or
R/(W)
LBT2
LDIV10
LDIV2
R/W
2
0
10
2
0
R/(W)
LBT1
LDIV1
LDIV9
R/W
1
0
1
9
0
R/(W)
LDIV0
LDIV8
LBT0
R/W
0
0
0
8
0
8209D–AVR–11/10
LINBRRL
LINBRRH
LINBTR
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