ATMEGA32M1-AU Atmel, ATMEGA32M1-AU Datasheet - Page 186
![MPU AVR 32K FLASH 20MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA32M1-AU
Manufacturer Part Number
ATMEGA32M1-AU
Description
MPU AVR 32K FLASH 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32M1-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32M1-AU
Manufacturer:
TYCO
Quantity:
210
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19.10.6
19.10.7
19.10.8
186
ATmega16M1/32M1/64M1
CANIE2 and CANIE1 – CAN Enable Interrupt MOb Registers
CANSIT2 and CANSIT1 – CAN Status Interrupt MOb Registers
CANBT1 – CAN Bit Timing Register 1
• Bits 5:0 - IEMOB[5:0]: Interrupt Enable by MOb
Note:
• Bit 15:6 –Res: Reserved
These bits are reserved for future use. For compatibility with future devices, it must be written to
zero when CANIE1 & CANIE2 are written.
• Bits 5:0 - SIT[5:0]: Status of Interrupt by MOb
Note:
• Bit 15:6 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 7– Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT1 is written.
Read/Write
Initial Value
Read/Write
Initial Value
Read/Write
Initial Value
Read/Write
Initial Value
Initial Value
Read/Write
– 0 - interrupt disabled
– 1 - MOb interrupt enabled
– 0 - no interrupt
– 1- MOb interrupt
Bit
Bit
Bit
Bit
Bit
Example: CANIE2 = 0000 1100
Example: CANSIT2 = 0010 0001
R/W
15
15
R
R
R
7
0
0
7
0
0
7
-
-
-
-
-
-
-
BRP5
R/W
R/W
R/W
14
14
R
R
6
0
0
6
0
0
6
0
-
-
-
-
IEMOB5
BRP4
SIT5
R/W
R/W
R/W
13
13
R
R
5
0
0
5
0
0
5
0
-
-
b
b
: enable of interrupts on MOb 2 and 3
: MOb 0 and 5 interrupts
IEMOB4
BRP3
SIT4
R/W
R/W
R/W
12
12
R
R
4
0
0
4
0
0
-
-
4
0
IEMOB3
BRP2
SIT3
R/W
R/W
R/W
11
11
R
R
3
0
0
3
0
0
3
0
-
-
IEMOB2
BRP1
SIT2
R/W
R/W
R/W
10
10
R
R
2
0
0
2
0
0
2
0
-
-
IEMOB1
BRP0
SIT1
R/W
R/W
R/W
R
R
1
9
0
0
1
9
0
0
-
-
1
0
IEMOB0
SIT0
R/W
R/W
R
R
0
8
0
0
0
8
0
0
0
-
-
-
-
-
8209D–AVR–11/10
CANSIT2
CANSIT1
CANBT1
CANIE2
CANIE1
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