ATMEGA32M1-AU Atmel, ATMEGA32M1-AU Datasheet - Page 204
![MPU AVR 32K FLASH 20MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA32M1-AU
Manufacturer Part Number
ATMEGA32M1-AU
Description
MPU AVR 32K FLASH 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32M1-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
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Manufacturer
Quantity
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Part Number:
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20.4.6.2
20.4.6.3
204
ATmega16M1/32M1/64M1
Tx Header Function
Rx & TX Response Functions
In accordance with the LIN protocol, only the master task must enable this function. The header
is sent in the appropriate timed slots at the programmed baud rate (c.f. LINBRR & LINBTR
registers).
The controller is responsible for:
At the end of this transmission, the controller automatically returns to Rx Header / LIN Abort
state (that is, LCMD[1..0] = 00) after setting the appropriate flags. This function leaves the con-
troller in the same setting as after the Rx Header function. This means that, in LIN 1.3, the
LINDLR register is set with the uncoded length value at the end of the Tx Header function.
During this function, the controller is also responsible for:
These functions are initiated by the slave task of a LIN node. They must be used after sending
an header (master task) or after receiving an header (considered as belonging to the slave task).
When the TX Response order is sent, the transmission begins. A Rx Response order can be
sent up to the reception of the last serial bit of the first byte (before the stop-bit).
In LIN 1.3, the header slot configures the LINDLR register. In LIN 2.1, the user must configure
the LINDLR register, either LRXDL[3..0] for Rx Response either LTXDL[3..0] for Tx Response.
When the command starts, the controller checks the LIN13 bit of the LINCR register to apply the
right rule for computing the checksum. Checksum calculation over the DATA bytes and the
PROTECTED IDENTIFIER byte is called enhanced checksum and it is used for communication
with LIN 2.1 slaves. Checksum calculation over the DATA bytes only is called classic checksum
and it is used for communication with LIN 1.3 slaves. Note that identifiers 60 (0x3C) to 63 (0x3F)
shall always use classic checksum.
At the end of this reception or transmission, the controller automatically returns to Rx Header /
LIN Abort state (that is LCMD[1..0] = 00) after setting the appropriate flags.
If an LIN error occurs, the reception or the transmission is stopped, the appropriate flags are set
and the LIN bus is left to recessive state.
During these functions, the controller is responsible for:
While the controller is sending or receiving a response, BREAK and SYNCH fields can be
detected and the identifier of this new header will be recorded. Of course, specific errors on the
previous response will be maintained with this identifier reception.
• The transmission of the BREAK field - 13 dominant bits
• The transmission of the SYNCH field - character 0x55
• The transmission of the PROTECTED IDENTIFIER field. It is the full content of the LINIDR
• The starting of the Frame_Time_Out
• The checking of the LIN communication integrity
• The initialization of the checksum operator
• The transmission or the reception of ‘
• The transmission or the checking of the CHECKSUM field
• The checking of the Frame_Time_Out
• The checking of the LIN communication integrity
register (automatic check bits included)
n
’ data with the update of the checksum calculation
8209D–AVR–11/10
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