AT91SAM7S64C-AU Atmel, AT91SAM7S64C-AU Datasheet - Page 642
AT91SAM7S64C-AU
Manufacturer Part Number
AT91SAM7S64C-AU
Description
IC ARM7 MCU 32BIT 64K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7S16-MU.pdf
(779 pages)
Specifications of AT91SAM7S64C-AU
Package / Case
64-LQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
55MHz
Number Of I /o
32
Core Processor
ARM7
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, SPI, SSC, UART/USART, USB
Core Size
16/32-Bit
Core
ARM7TDMI
Package
64LQFP
Device Core
ARM7TDMI
Family Name
AT91
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
32
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7S64B-AU::AT91SAM7S64B-AU
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7S64C-AU
Manufacturer:
ATMEL
Quantity:
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Part Number:
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Manufacturer:
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40.8.8.5
40.8.9
40.8.9.1
40.8.9.2
40.8.9.3
40.8.9.4
40.8.9.5
642
AT91SAM7S Series Preliminary
Universal Synchronous Asynchronous Receiver Transmitter (USART)
TWI: Possible Receive Holding Register Corruption
USART: CTS in Hardware Handshaking
USART: Hardware Handshaking – Two Characters Sent
USART: XOFF Character Bad Behavior
USART: RXBRK Flag Error in Asynchronous Mode
USART: DCD is active High instead of Low
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of
the TWI_SR.
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the
TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor
OVERRUN status bits are set if this occurs.
The user must be sure that received data is read before transmitting any new data.
When Hardware Handshaking is used and if CTS goes low near the end of the starting bit, a
character can be lost.
CTS must not go low during a time slot occurring between 2 Master Clock periods before the
starting bit and 16 Master Clock periods after the rising edge of the starting bit.
If CTS switches from 0 to 1 during the TX of a character and if the holding register (US_THR) is
not empty, the content of US_THR will also be transmitted.
Don't use the PDC in transmit mode and do not fill US_THR before TXEMPTY is set at 1.
The XOFF character is sent only when the receive buffer is detected full. While the XOFF is
being sent, the remote transmitter is still transmitting. As only one Holding register is available in
the receiver, characters will be lost in reception. This makes the software handshaking function-
ality ineffective.
None.
In receiver mode, when there are two consecutive characters (without timeguard in between),
RXBRK is not taken into account. As a result, the RXBRK flag is not enabled correctly and the
frame error flag is set.
Constraints on the transmitter device connected to the AT91SAM7S USART receiver side:
The transmitter may use the timeguard feature or send two STOP conditions. Only one STOP
condition is taken into account by the receiver state machine. After this STOP condition, as there
is no valid data, the receiver state machine will go in idle mode and enable the RXBRK flag.
The DCD signal is active at High level in the USART Modem Mode.
DCD should be active at Low level.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6175K–ATARM–30-Aug-10
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