AT91SAM7S64C-AU Atmel, AT91SAM7S64C-AU Datasheet - Page 362
AT91SAM7S64C-AU
Manufacturer Part Number
AT91SAM7S64C-AU
Description
IC ARM7 MCU 32BIT 64K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7S16-MU.pdf
(779 pages)
Specifications of AT91SAM7S64C-AU
Package / Case
64-LQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
55MHz
Number Of I /o
32
Core Processor
ARM7
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, SPI, SSC, UART/USART, USB
Core Size
16/32-Bit
Core
ARM7TDMI
Package
64LQFP
Device Core
ARM7TDMI
Family Name
AT91
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
32
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7S64B-AU::AT91SAM7S64B-AU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7S64C-AU
Manufacturer:
ATMEL
Quantity:
4 300
Part Number:
AT91SAM7S64C-AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 362 of 779
- Download datasheet (11Mb)
Table 31-2.
31.6.1.3
362
Source Clock
12 000 000
12 288 000
14 318 180
14 745 600
18 432 000
24 000 000
24 576 000
25 000 000
32 000 000
32 768 000
33 000 000
40 000 000
50 000 000
8 000 000
AT91SAM7S Series Preliminary
AT91SAM7S512/156/128 Fractional Baud Rate in Asynchronous Mode
Baud Rate Example (OVER = 0) (Continued)
Expected Baud
The baud rate is calculated with the following formula:
The baud rate error is calculated with the following formula. It is not recommended to work with
an error higher than 5%.
The Baud Rate generator previously defined is subject to the following limitation: the output fre-
quency changes by only integer multiples of the reference frequency. An approach to this
problem is to integrate a fractional N clock generator that has a high resolution. The generator
architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
This fractional part is programmed with the FP field in the Baud Rate Generator Register
(US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the
clock divider. This feature is only available when using USART normal mode. The fractional
Baud Rate is calculated using the following formula:
The modified architecture is presented below:
Baudrate
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
Rate
BaudRate
Error
=
=
1
------------------------------------------------------------------
⎛
⎝
–
8 2 Over
Calculation Result
⎛
⎝
(
=
ExpectedBaudRate
-------------------------------------------------------- -
SelectedClock
ActualBaudRate
–
MCK
13.02
19.53
20.00
23.30
24.00
30.00
39.06
40.00
40.69
52.08
53.33
53.71
65.10
81.38
⁄
) CD
⎛
⎝
CD
+
×
FP
------- -
8
16
⎞
⎠
⎞
⎠
⎞
⎠
CD
13
20
20
23
24
30
39
40
40
52
53
54
65
81
Actual Baud Rate
38 461.54
37 500.00
38 400.00
38 908.10
38 400.00
38 400.00
38 461.54
38 400.00
38 109.76
38 461.54
38 641.51
38 194.44
38 461.54
38 580.25
6175K–ATARM–30-Aug-10
0.16%
2.40%
0.00%
1.31%
0.00%
0.00%
0.16%
0.00%
0.76%
0.16%
0.63%
0.54%
0.16%
0.47%
Error
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