USBLC6-4SC6 STMicroelectronics, USBLC6-4SC6 Datasheet - Page 4

• Manufacturer Part Number: USBLC6-4SC6
• Description: IC ESD PROTECTION HS SOT23-6
• Manufacturer: STMicroelectronics

Specifications of USBLC6-4SC6

• Voltage - Working: 5V
• Voltage - Clamping: 6V
• Technology: Mixed Technology
• Number Of Circuits: 4
• Applications: USB
• Package / Case: SOT-23-6
• Polarity: Bidirectional
• Channels: 4 Channels
• Clamping Voltage: 17 V
• Operating Voltage: 5 V
• Breakdown Voltage: 6 V
• Termination Style: SMD/SMT
• Peak Surge Current: 5 A
• Capacitance: 3.5 pF
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Dimensions: 1.75 mm W x 3.05 mm L x 1.45 mm H
• Diode Type: ESD Protection
• Clamping Voltage Vc Max: 17V
• Diode Case Style: SOT-23
• No. Of Pins: 6
• Standoff Voltage: 5V
• Filter Terminals: SMD
• Breakdown Voltage Min: 6V
• Rohs Compliant: Yes
• Clamping Voltage 8/20us Max: 17V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-4492-2

Technical information
2
2.1
Note:
2.2
4/13
Technical information
Surge protection
The USBLC6-4SC6 is particularly optimized to provide surge protection based on the rail to
rail topology.
The clamping voltage V
with: V
(V
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically:
For an IEC 61000-4-2 surge level 4 (Contact Discharge: V
V
So, we find:
The calculations do not take into account phenomena due to parasitic inductances.
Surge protection application example
If we consider that the connections from the pin V
from GND to PCB GND plane are implemented as racks 10 mm long and 0.5 mm large, we
can assume that the parasitic inductances L
6 nH. So, when an IEC 61000-4-2 surge occurs, due to the rise time of this spike (t
the voltage V
The dI/dt is calculated as:
The overvoltage due to the parasitic inductances is:
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be:
We can significantly reduce this phenomena with simple layout optimization. It is for this
reason that some recommendations have to be followed (see
protection).
BUS
F
forward drop voltage, V
V
V
R
I
V
V
dI/dt = I
L
V
V
p
= +5 V, and if in a first approximation, we assume that:
I/0
CL
CL
CL
CL
CL
CL
d
F
= V
= 0.5
·dI/dt, = L
+ = V
- = - V
= V
+ = +31.2 V
- = -13.1 V
+ = +31.2 + 144 + 144 = 319.2 V
- = -13.1 - 144 -144 = -301.1 V
g
T
/ R
p
CL
/t
+ R
TRANSIL
r
g
= 24 A/ns
F
has an extra value equal to L
and V
= 24 A.
d
GND
for negative surges
.I
p
·dI/dt = 6 x 24 = 144 V
T
+ V
CL
= 1.1 V.
F
can be calculated as follows:
T
for positive surges
forward drop threshold voltage
VBUS
I/0
·dI/dt, + L
L
BUS
I/0
and L
to V
GND
CC
g
GND
= 8 kV, R
, from from I/O to data line and
·dI/dt
2.3: How to ensure good ESD
of these tracks are about
g
= 330
),
USBLC6-4
r
= 1 ns),