SAK-C868-1SR BA Infineon Technologies, SAK-C868-1SR BA Datasheet - Page 63

• Manufacturer Part Number: SAK-C868-1SR BA
• Description: IC MCU 8BIT 8KB RAM TSSOP-38-1
• Manufacturer: Infineon Technologies
• Series: C5xx/C8xxr

Specifications of SAK-C868-1SR BA

• Core Processor: C800
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: RAM
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SAKC8681SRBAXT; SP000014357

C868
Fail Save Mechanisms
The C868 offers enhanced fail save mechanisms, which allow an automatic recovery
from software upset or hardware failure :
a programmable watchdog timer (WDT), with variable time-out period from 12.8 s to
819.2 s at f
.
= 40 MHz
SYS
Programmable Watchdog Timer
To protect the system against software failure, the user’s program has to clear this
watchdog within a previously programmed time period. lf the software fails to do this
periodical refresh of the watchdog timer, an internal reset will be initiated. The software
can be designed so that the watchdog times out if the program does not work properly.
lt also times out if a software error is based on hardware-related problems.
The watchdog timer in the C868 is a 16-bit timer, which is incremented by a count rate
of f
/2 upto f
/128. The machine clock of the C868 is divided by a prescaler, a divide-
SYS
SYS
by-two or a divide-by-128 prescaler. The upper 8 bits of the Watchdog Timer can be
preset to a user-programmable value via a watchdog service access in order to vary the
watchdog expire time. The lower 8 bits are reset on each service access.
Figure 29
shows the block diagram of the watchdog timer unit.
WDT
WDTREL
Control
Clear
1:2
MUX
WDTRST
WDT High Byte
WDT Low Byte
f
SYS
1:128
DISWDT
WDTIN
Figure 29
Block Diagram of the Programmable Watchdog Timer
After a reset, the Watchdog Timer is automatically enabled. If it is disabled, it cannot be
enabled again during active mode of the device. If the software fails to clear the
watchdog timer an internal reset will be initiated. The reset cause (external reset or reset
caused by the watchdog) can be examined by software (status flag WDTR in SCUWDT
is set). A refresh of the watchdog timer is done by setting bits WDTRE and WDTRS (in
Data Sheet
63
V 1.0, 2003-05