SAK-C868-1SR BA Infineon Technologies, SAK-C868-1SR BA Datasheet
SAK-C868-1SR BA
Specifications of SAK-C868-1SR BA
SP000014357
Related parts for SAK-C868-1SR BA
SAK-C868-1SR BA Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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C868 Revision History: Previous Version: Page Subjects (major changes since last revision) Current data updated Description of I2C included We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your ...
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Single-Chip Microcontroller C800 Family C868 Advance Information • C800 core : –Fully compatible to standard 8051 microcontroller –Superset of the 8051 architecture with 8 datapointers • 40 MHz internal CPU clock –external clock of 6.67 - 10.67 MHz at ...
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... Single power supply of 3.3V, internal voltage regulator for core voltage of 2.5V. • P-DSO-28-1, P-TSSOP-38-1 packages • Temperature ranges: SAF-C868-1RR BA, SAF-C868-1SR BA, SAF-C868-1RG BA, SAF-C868-1SG BA, SAF-C868A-1RR BA, SAF-C868A-1SR BA, SAF-C868A-1RG BA, SAF-C868A-1SG BA, SAF-C868P-1SR BA, SAF-C868P-1SG BA T SAK-C868-1RR BA, SAK-C868-1SR BA, SAK-C868-1RG BA, SAK-C868-1SG BA, SAK-C868A-1RR BA, SAK-C868A-1SR BA, SAK-C868A-1RG BA, SAK-C868A-1SG BA, SAK-C868P-1SR BA, SAK-C868P-1SG BA T Data Sheet o = – ...
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V AREF V AGND RESET ALE/BSL CTRAP TxD RxD Figure 2 Logic Symbol Data Sheet V V DDP SSP Port 1 5-bit Digital I/O 3-bit Digial Input Port 3 8-bit Digital I/O C868 5 ADC channels 4 External Interrupts V ...
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P1.4/RxD P1.3/INT3 P1.1/EXF2 P1.0/TxD P1.5/CCPOS0/T2/INT0/AN0 P1.6/CCPOS1/T2EX/INT1/AN1 P1.7/CCPOS2/INT2/AN2 Figure 3 C868 Pin Configuration P-TSSOP-38 Package (top view) P3.4/COUT61 P3.0/COUT63 P3.1/CTRAP ALE/BSL P3.6/COUT60 P3.7/CC60 P1.4/RxD P1.3/INT3 P1.1/EXF2 P1.0/TxD Figure 4 C868 Pin Configuration P-DSO-28 Package (top view) Data Sheet ...
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Table 1 Pin Definitions and Functions Symbol Pin Numbers P- P- DSO- TSSOP P1.0– 12-8 6,4-1 P1.4 P1.5- 15-17 11-13 P1 *)I=Input ...
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Table 1 Pin Definitions and Functions Symbol Pin Numbers P- P- DSO- TSSOP P3.0– 2,3,23, 32,33,25, P3.7 24,1, 26,31,24, 22,5,6 36, ...
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Table 1 Pin Definitions and Functions Symbol Pin Numbers P- P- DSO- TSSOP SSC DDC NC – 5,7,8,18, 19,20,21, 22,23,35 XTAL1 27 29 XTAL2 28 30 *)I=Input O=Output Data Sheet I/O*) Function ...
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V DDC C868 V SSC XTAL1 OSC XTAL2 PLL CPU RESET 8 datapointers Programmable Watchdog Timer Timer 0 Timer 1 Timer 2 UART Capture/Compare Unit 4 external Interrupt Unit interrupts V AREF A/D Converter V 8-Bit AGND 5-Bit Analog In ...
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CPU The C868 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C868 CPU manipulates operands in the following five address spaces: – Kbyte of RAM internal program memory : 8K ROM for C868-1R – 4 Kbyte of internal Self test and Boot ROM – 256 ...
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The various chip modes supported are shown in Bootstrap Mode Hardware Software Figure 6 Entry and exit of Chip Modes A valid hardware reset would, of course, override any of the above entry or exit procedures. Table 0-1 Hardware and ...
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Table 3 Normal Memory Configuration Chip Memory Space Mode Normal Code Space Internal Data Space Bootstrap Code Space Internal Data Space Normal Code Space XRAM Data Space Bootstrap Code Space XRAM Data Space Data Sheet Memory Boundary ROM/RAM: 0000 to ...
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Bootstrap loader The C868, includes a bootstrap mode, which is activated by setting the ALE/BSL pin at logic low with a pulldown and TxD pin at logic high with a pullup at the rising edge of the RESET ...
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Read serial EEPROM (first byte) Yes Phase A byte=A5 Bootstrap from serial EEPROM Activate mode 0 Activate Mode 1 Load custom code Execute custom to SRAM/XRAM program in XRAM Figure 7 The phases of the Bootstrap Loader The serial communication ...
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P1.3 /CS 6 P1.1 SCK 5 P1 240R a) SPI EEPR OM connection Figure 9 EEPROM connections for a) SPI and b) I2C Data Sheet / ...
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Reset and Brownout The reset input is an active low input. An internal Schmitt trigger is used at the input for noise rejection. The RESET pin must be held low for at least tbd usec. But the CPU will only ...
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Clock system The C868 clock system consist of the on-chip oscillator, PLL and multiplexer stage. The programmable Slow Down Divider (SDD) divides the PLL output clock frequency by a factor of 1...32 which is specified via CMCON.REL. The system clock ...
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The PLL output frequency is determined by: The range for the VCO frequency is given by: 100 MHz The relationship between the input frequency and VCO frequency is given by: This gives the range for the input frequency which is ...
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Figure 12 shows the recommended oscillator circuitries for crystal and external clock operation. Crystal Oscillator Mode 6.67-10.67 MHz for crystal operation (incl. StrayCapacitance) Figure 12 Recommended Oscillator Circuit In this application the on-chip oscillator ...
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XTAL1 *) Crystal or ceramic resonator Figure 13 On-Chip Oscillator Circuitry To drive the C868 with an external clock source, the external clock signal has to be applied to XTAL2, as shown in resistor is suggested (to increase the noise ...
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Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and ...
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Table 6 Special Function Registers - Functional Blocks Block Symbol Name C800 ACC Accumulator core B B-Register DPH Data Pointer, High Byte DPL Data Pointer, Low Byte DPSEL Data Pointer Select Register PSW Program Status Word Register SP Stack Pointer ...
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Table 6 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name A/D- ADCON0 A/D Converter Control Register 0 Con- ADCON1 A/D Converter Control Register 1 verter ADDATH A/D Converter Data Register Ports P1 Port 1 Register 4) P1DIR Port ...
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Table 6 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Cap- T12L Timer T12 Counter Register, Low Byte ture/ T12H Timer T12 Counter Register, High Byte Com- T13L Timer T13 Counter Register, Low Byte pare T13H Timer T13 ...
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Table 6 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Cap- ISSL Cap/Com Int Status Set Reg, Low Byte 3) ture/ ISSH Cap/Com Int Status Set Reg, High Byte 3) Com- ISRL Cap/Com Int Status Reset Reg, Low ...
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Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- Content Bit 7 after ister 1) Reset DPL DPH ...
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Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- Content Bit 7 after ister 1) Reset A2 WDTC XXXX – XX00 B A3 WDTR PSLRL 00 ...
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Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- Content Bit 7 after ister 1) Reset B8 IP0 XX00 – H 0000 B BB PISEL 00 – ISSL 00 ST12P ...
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Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- Content Bit 7 after ister 1) Reset C6 CC62 CC62 T2CO 00 TF2 ...
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Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- Content Bit 7 after ister 1) Reset D7 MODC 00 ECT13 TRH O D8 ADCO 00 ADST ADBS ...
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Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- Content Bit 7 after ister 1) Reset E6 T12DT T12DT 00 – PMCO XXXX – H ...
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Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- Content Bit 7 after ister 1) Reset F8 PMCO XXXX – X000 B F9 VERSI 00 PROT VER6 VER5 VER4 VER3 VER2 VER1 ...
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Ports The C868 has two kinds of ports. The first kind is push-pull ports instead of the traditional quasi-bidirectional ports. The ports belonging to this kind are lsb of port 1 which bit I/O port and port ...
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Timer 0 and 1 Timer 0 and 1 can be used in four operating modes as listed in Table 8 Timer 0 and 1 Operating Modes Mode Description 0 8-bit timer with a divide-by-32 prescaler 1 16-bit timer 2 8-bit ...
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Timer/Counter 2 with Compare/Capture/Capture Timer 16-bit timer/counter with an up/down count feature. It has three operating modes: • 16-bit auto-reload mode (up or down counting) • 16-bit capture mode • Baudrate generator Table 9 Timer/Counter 2 Operating ...
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Serial Interface (UART) The serial port is a full duplex port capable of simultaneous transmit and receive functions also receive-buffered; it can commence reception of a second byte before a previously-received byte has been read from the receive ...
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The baudrates in Mode 1 and 3 are determined by the timer overflow rate. These baudrates can be determined by Timer Timer 2 or both (one for transmit, the other for receive. Table 11 Serial Interface - ...
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Capture/Compare Unit (CCU6) The CCU6 provides two independent timers (T12, T13), which can be used for PWM generation, especially for AC-motor control. Additionally, special control modes for block commutation and multi-phase machines are supported. Timer 12 Features • Three capture/compare ...
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Switching Examples T12P T12P-1 T12P-2 compare-match = period-match zero-match 0 1 < T12P-3 active T12 shadow transfer Figure 16 Edge-aligned mode with duty cycles near 100% and near 0%. Applicable to T13 as well. compare-match ...
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Dead-time Generation The dead-time generation logic is built in a similar way for all three channels of T12. Each of the three channels works independently with its own dead-time counter and the trigger and enable signals. Figure 18 Dead-time generation ...
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Single Shot Mode In single shot mode, the timer T12 stops automatically at the end of the its counting period. edge-aligned mode T12P T12P-1 T12P-2 if T12SSC = ’1’ Figure 19 Single Shot Mode of T12, T13 is edge-aligned mode ...
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Synchronization of T13 to T12 The timer T13 can be synchronized on a T12 event. Combined with the single shot mode, this feature can be used to generate a programmable delay after a T12 event. compare-match while T12 0 T13 ...
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Trap Handling The trap functionality permits the PWM outputs to react on the state of the input pin CTRAP. This functionality can be used to switch off the power devices if the trap input becomes active (e.g. as emergency stop). ...
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Modulation control The modulation control part combines the different modulation sources, six T12-related signals from the three compare channels, the T13-related signal and the multi-channel modulation signals. each modulation source can be individually enabled for each output line. Furthermore, the ...
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Hall Sensor Mode In Brushless-DC motors the next multi-channel state values depend on the pattern of the Hall inputs. There is a strong correlation between the Hall pattern (CURH) and the modulation pattern (MCMP). Because of different machine types the ...
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Below is a table listing output (MCMP) for a BLDC motor. Block Commutation Control Table Mode CCPOS0- CCPOS2 Inputs CCP CCP OS0 OS1 Rotate left phase shift ...
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For Brushless-DC motors there is a special mode (MSEL6x = ’1000b’) which is triggered by a change of the Hall-inputs (CCPOSx). This mode shows the capabilities of the CCU6. Here T12’s channel 0 acts in capture function, channel 1 and ...
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A/D Converter The C868 includes a high performance / high speed 8-bit A/D-Converter (ADC) with 5 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. ...
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Conversion and sample time control The conversion and sample times are programmed via the bit fields ADCTC and ADSTC respectively of the register ADCON1. Bit field ADCTC (conversion time control) ...
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Interrupt System The C868 provides 13 interrupt vectors with four priority levels. Nine interrupt requests are generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial channel, A/D converter, and the capture/compare unit with 4 interrupts) and four ...
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ICC60R ENCC60R P3.7/ ISL.0 IENL.0 CC0 ICC60F ENCC60F ISL.1 IENL.1 ICC61R ENCC61R ISL.2 P3.5/ IENL.2 CC1 ICC61F ENCC61F ISL.3 IENL.3 ICC62R ENCC62R ISL.4 P3.3/ IENL.4 CC2 ICC62F ENCC62F ISL.5 IENL.5 T12 T12OM One Match ENT12OM ISL.6 IENL.6 T12 T12PM ENT12PM ...
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INT0_ IE0 CORE_N (CCPOS / TCON.1 IT0 T2 / INT0 / TCON.0 AN0) A/D Converter IADC IRCON1.0 Timer 0 TF0 Overflow TCON.5 CCPOS2 / INT2 / EX2 AN2 IRCON0.0 ESEL2 EXICON.0 Bit addressable Request flag is cleared by hardware Figure ...
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CCPOS1 / IE1 T2EX / INT1 / TCON.3 AN1 IT1 TCON.2 EXINT3 P1.3 / INT3 IRCON0.1 ESEL3 EXICON.1 INP0 Capture/compare interrupt node 0 IRCON1.2 Bit addressable Request flag is cleared by hardware Figure 25 Interrupt Structure, Overview Part 2 Data ...
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Timer 1 TF1 Overflow TCON.7 Capture/compare INP1 interrupt node 1 IRCON1.3 Bit addressable Request flag is cleared by hardware Figure 26 Interrupt Structure, Overview Part 3 Data Sheet 001B H ET1 IEN0.3 008B H EINP1 IEN2.3 EA IP1.3 IP0.3 IEN0.7 ...
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RI UART SCON.0 TI SCON.1 Capture/compare INP2 interrupt node 2 IRCON1.4 Bit addressable Request flag is cleared by hardware Figure 27 Interrupt Structure, Overview Part 4 Data Sheet 1 0023 H ES IEN0.4 0093 H EINP2 IEN2.4 IP1.4 EA IEN0.7 ...
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Timer 2 TF2 Overflow IRCON0.6 INP3 Capture/compare interrupt node 3 IRCON1.5 Bit addressable Request flag is cleared by hardware Figure 28 Interrupt Structure, Overview Part 5 Data Sheet 002B H ET2 IEN0.5 009B H EINP3 IEN2.5 IP1.5 EA IEN0.7 60 ...
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Table 12 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow A/D Converter External Interrupt 2 External Interrupt 3 CAPCOM interrupt node 0 CAPCOM interrupt node ...
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lf two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. lf requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to ...
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Fail Save Mechanisms The C868 offers enhanced fail save mechanisms, which allow an automatic recovery from software upset or hardware failure : a programmable watchdog timer (WDT), with variable time-out period from 12 819 ...
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SFR SCUWDT) consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the watchdog timer is halted during the idle mode and power-down mode of the processor (see section "Power Saving Modes"). ...
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Power Saving Modes The C868 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and ...
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Table 15 Power Saving Modes Overview Mode Entering Idle ORL PCON,#01 Mode Slow In normal mode: Down ORL PCON,#10 Mode With idle mode: ORL PCON,#11 Software With external wake-up Power capability from power down Down enabled mode ORL PMCON0,#01 (to ...
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Device Specifications Absolute Maximum Ratings Absolute Maximum Rating Parameters Parameter Ambient temperature under bias Storage temperature Voltage on V pins with respect DDP to ground ( V ) SSP Voltage on any pin except int/ analog and XTAL with respect ...
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... AIN AGND AREF 6.67 10. |20 > +0.5V or < OV DDP OV SSP V DDP 68 Unit Notes max. V Active mode MHz SYSmax V PowerDown 1) mode V - °C SAF-C868... °C SAK-C868... + MHz - -0.5V). The absolute sum of input currents and V must remain within the specified SSP V 1.0, 2003-05 C868 ...
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Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. port pins may not exceed 20mA. The suply voltages 5) Overload conditions under operating conditions occur if the voltage on ...
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... XTAL1 = N.C.; DDP SSC pin. DDC ,max trace length to capacitor is 10mm. 70 C868 Unit Test Condition 1) – V DDP V DDC V DDC – +0.5 V +0 SAF-C868... I =10mA OL V SAK-C868... I =10mA =10mA OH uA 0.4<V <V IN DDP uA 0.4<V <V IN DDP uA 0.4<V <V IN DDC V – – ...
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... DDP 71 Unit Test Condition 2) max. 4) 15 9 4 4.2 mA 4.1 mA 300 uA SAF-C868... SAK-C868... 400 uA SAF-C868... 300 uA SAK-C868... 400 – and V A DDP , – 0.5 V; XTAL1 = N.C.; IH2 DDP V 1.0, 2003-05 C868 3.6 V). ...
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I (idle mode) is measured with all output pins disconnected and with all peripheral disabled: DDP XTAL2 driven with ns RESET = V ; all other pins are disconnected. DDP 6) I ...
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Power Supply Current Calculation Formulae Parameter Active mode C868-1S C868-1R Idle mode C868-1S C868-1R Active mode with C868-1S slow-down enabled C868-1R Idle mode with slow- C868-1S down enabled C868- MHz and results in mA. SYS Data ...
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A/D Converter Characteristics (Operating Condition Parameters) Parameter Symbol Analog input voltage V Sample time t Conversion cycle time t Total unadjusted error T ADC input resistance R ADC input capacitance C ADC reference pin C capacitance Note ...
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During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach their final voltage level within After the end of the sample time 5) Not 100% tested, but guaranteed by design ...
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Clock calculation table for ADC 1) TVC 2) STC 322 386 ADCC t 64 128 S 1) TVC 2) STC 282 338 ADCC t 56 112 S 1) TVC 2) STC ...
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TVC 2) STC ADCC TVC 2) STC ADCC TVC is the clock divider specified by bit fields ADCTC. 2) ...
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AC Characteristics (Operating Condition Apply) External Clock Drive Characteristics Parameter Oscillating period High time Low time Rise time Fall time ALE Characteristics Parameter ALE pulse width ALE period Data Sheet Symbol Limit Values Variable Ext Clock 6.67 to 10.67 MHz ...
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Figure 30 External Clock Drive on XTAL2 t AWD Figure 31 ALE Characteristic Data Sheet OSC t ACY 79 C868 MCT04105 ...
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... Package Outlines Plastic Package, P-DSO-28-1 for SAF-C868-1RG BA, SAF-C868-1SG BA SAF-C868A-1RG BA, SAF-C868A-1SG BA and SAF-C868P-1SG BA, SAK-C868-1RG BA, SAK-C868-1SG BA, SAK-C868A-1RG BA, SAK-C868A-1SG BA and SAK-C868P-1SG BA. 1.27 +0. Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side ...
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... Plastic Package, P-TSSOP-38-1 for SAF-C868-1RR BA, SAF-C868-1SR BA, SAF-C868A-1RR BA, SAF-C868A-1SR BA, SAF-C868P-1SR BA, SAK-C868-1RR BA, SAK-C868-1SR BA, SAK-C868A-1RR BA, SAK-C868A-1SR BA, and SAK-C868P-1SR BA. 0.5 +0.07 2) 0.2 -0. Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.08 max. per side 3) Does not include plastic or metal protrusion of 0.25 max. per side ...
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