DS89C420-ENG Maxim Integrated Products, DS89C420-ENG Datasheet - Page 39

• Manufacturer Part Number: DS89C420-ENG
• Description: IC MCU ULTRA 25MHZ HP 44-TQFP
• Manufacturer: Maxim Integrated Products
• Series: 89Cr

Specifications of DS89C420-ENG

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

WATCHDOG TIMER
The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. When the clock
divider is set to 10b, the interrupt timeout has a default divide ratio of 2
watchdog reset set to timeout 512 system clock cycles later. This results in a 33MHz crystal oscillator producing an
interrupt timeout every 3.9718ms, followed 15.5µs later by a watchdog reset. The watchdog timer is reset to the
default divide ratio following any reset. Using the WD0 and WD1 bits in the clock control (CKCON.6 and 7) register,
other divide ratios can be selected for longer watchdog interrupt periods.
settings and the timeout values.
Note: All watchdog-timer reset timeouts follow the programmed interrupt timeouts by 512 system clock cycles,
which equates to varying numbers of oscillator cycles depending on the clock-divide (CD1:0) and crystal multiplier
settings.
Table 13. Watchdog Timeout Value (in Number of Oscillator Clocks)
A watchdog control (WDCON) SFR is used for programming the functions. EWT (WDCON.1) is the enable for the
watchdog-timer reset function and RWT (WDCON.0) is the bit used to restart the watchdog timer. Setting the RWT
bit restarts the timer for another full interval. If the watchdog timer reset function is masked by the EWT bit and no
resets are issued to the timer through the RWT bit, the watchdog timer generates interrupt timeouts at a rate
determined by the programmed divide ratio. WDIF (WDCON.3) is the interrupt flag set at timer termination and
WTRF (WDCON.2) is the reset flag set following a watchdog-reset timeout. The watchdog interrupt is enabled by
the EWDI bit (EIE.4) when it is set to 1. The watchdog timer reset and interrupt timeouts are measured by counting
system clock cycles.
An independent watchdog timer functions as the crystal startup counter to count 65,536 crystal clock cycles before
allowing the crystal oscillator to function as the system clock. This warmup time is verified by the watchdog timer
following each power-up as well as each time the crystal is restarted following a stop mode. The watchdog is also
used to establish a startup time whenever the CTM in the PMR register is set to enable the crystal multiplier
(4X / 2X ).
One of the applications of the watchdog timer is for the watchdog to wake up the system from idle mode. The
watchdog interrupt can be programmed to allow a system to wake up periodically to sample the external world.
EXTERNAL RESET
If the RST input is taken to a logic 1, the device is forced into a reset state. An external reset is accomplished by
holding the RST pin high for at least 3 clock cycles while the oscillator is running. Once the reset state is invoked, it
is maintained as long as RST is pulled to logic 1. When the RST is removed, the processor exits the reset state
within 4 clock cycles and begins execution at address 0000h. If a RST is applied while the processor is in stop
mode, the RST causes the oscillator to begin running and forces the program counter to 0000h. There is a reset
delay of 65,536 clock cycles to allow the oscillator to stabilize.
The RST pin is a bidirectional I/O. If a reset is caused by a power-fail reset, a watchdog timer reset, or an internal
system reset, an output-reset pulse is also generated at the RST pin. This reset pulse is asserted as long as an
internal reset is asserted and may not be able to drive the reset signal out if the RST pin is connected to an RC
circuit. Connecting the RST pin to a capacitor does not affect the internal reset condition.
4X/2X
1
0
x
x
x
CD1:0
00
00
01
10
11
WD1:0 = 00 WD1:0 = 01 WD1:0 = 10 WD1:0 = 11
2
2
2
2
2
15
16
17
17
27
WATCHDOG INTERRUPT TIMEOUT
2
2
2
2
2
18
19
20
20
30
2
2
2
2
2
21
22
23
23
33
2
2
2
2
2
39 of 47
24
25
26
26
36
2
27
WD1:0 = 00
2
2
2
2
15
16
17
17
+ 524,288 2
+ 128
+ 256
+ 512
+ 512
17
WATCHDOG RESET TIMEOUT
Table 13
30
of the crystal oscillator clock, with the
WD1:0 = 01
2
2
2
2
18
19
20
20
+ 524,288 2
+ 128
+ 256
+ 512
+ 512
summarizes the watchdog bit
WD1:0 = 10
33
2
2
2
2
+ 524,288 2
21
22
23
23
+ 128
+ 256
+ 512
+ 512
36
WD1:0 = 11
2
2
2
2
24
25
26
26
+ 524,288
+ 128
+ 256
+ 512
+ 512