DS89C420-ENG Maxim Integrated Products, DS89C420-ENG Datasheet - Page 38

• Manufacturer Part Number: DS89C420-ENG
• Description: IC MCU ULTRA 25MHZ HP 44-TQFP
• Manufacturer: Maxim Integrated Products
• Series: 89Cr

Specifications of DS89C420-ENG

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

simplified diagram of the generation of the system clocks. Specifics of hardware restrictions associated with the
use of the 4X/ 2X CTM, CKRY, CD1, and CD0 bits are outlined in the SFR description.
Figure 15. System Clock Sources
BANDGAP-MONITORED INTERRUPT AND RESET GENERATION
The power monitor in the DS89C420 monitors the V
Whenever V
(WDCON.5) is set, causing the device to vector to address 33h. The power-fail interrupt-status bit PFI (WDCON.4)
is set anytime V
below V
power-on reset timeout before starting program execution. When V
processor is held in reset until V
is within tolerance and the clock source has had time to stabilize. Once the reset timeout period has elapsed, the
reset condition is removed automatically and software execution begins at the reset vector location of 0000h. The
power-on reset flag POR (WDCON.6) is set to logic 1 to indicate a power-on reset has occurred, and can only be
cleared by software.
When the DS89C420 enters stop mode, the bandgap, reset comparator, and power-fail interrupt comparator are
automatically disabled to conserve power, if the BGS (EXIF.0) bit is set to a logic 0. This is the lowest power mode.
If BGS is set to logic 1, the bandgap reference, reset comparator, and the power-fail comparator are powered up,
although in a reduced fashion, while in stop mode.
RST
Oscillator
, a reset is issued internally to halt program execution. Following power-up, a power-on reset initiates a
Crystal
CC
falls below V
CC
transitions below V
PFW
Ring
Enable
, an interrupt is generated if the corresponding power-fail interrupt-enable bit EPFI
CC
4X/2X
CTM
> V
RST
PFW
and a delay of 65,536 oscillator cycles has elapsed, to ensure that power
, and can only be cleared by software once set. Similarly, as V
Divide 1024
Multiplier
Oscillator
Clock
Ring
38 of 47
CC
pin in relation to the on-chip bandgap voltage reference.
CD0
CD1
CC
is first applied to the DS89C420, the
Selector
MUX
System
Clock
CC
falls