MCF54455CVR200 Freescale Semiconductor, MCF54455CVR200 Datasheet - Page 27

• Manufacturer Part Number: MCF54455CVR200
• Description: IC MPU 32BIT 200MHZ 360TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF5445xr

Specifications of MCF54455CVR200

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 132
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 360-TEPBGA
• Processor Series: MCF544x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 16 KB
• Data Ram Size: 32 KB
• Interface Type: I2C, SPI, SSI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M54455EVB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 16 Channel
• On-chip Dac: 16 bit, 16 Channel
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• For Use With: M54455EVB - BOARD EVAL FOR MCF5445X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.9
The PCI bus on the device is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Refer to the
PCI 2.2 spec for a more detailed timing analysis.
Freescale Semiconductor
Num
P1
P2
P3
P4
P5
Frequency of Operation
Clock Period
Bused PCI signals — input setup
PCI_GNT[3:0]/PCI_REQ[3:0] — input setup
All PCI signals — input hold
Bused PCI signals — output valid
SD_DQS3/SD_DQS2
SD_DQS3/SD_DQS2
PCI Bus Timing Specifications
D[31:24]/D[23:16]
SD_RAS, SD_CAS
SD_CSn,SD_WE,
D[31:24]/D[23:16]
SD_A[13:0]
SD_CLK
SD_CLK
MCF5445x ColdFire
DD4
Characteristic
Table 14. PCI Timing Specifications
ROW
CMD
Figure 12. DDR Read Timing
DD1
®
DD5
Microprocessor Data Sheet, Rev. 6
COL
CL=2
CL=2.5
DD2
DQS Read
Preamble
DD10
10.0
1
Min
7.0
30
—
—
,
0
2
DQS Read
33 MHz
DD3
Preamble
33.33
Max
11.0
WD1 WD2 WD3 WD4
3
—
—
—
—
WD1 WD2 WD3 WD4
DD9
Electrical Characteristics
33.33
Min
3.0
5.0
15
—
0
66 MHz
DQS Read
Postamble
66.66
Max
6.0
30
3
—
—
—
DQS Read
Postamble
MHz
Unit
ns
ns
ns
ns
ns
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