mcf54455 Freescale Semiconductor, Inc, mcf54455 Datasheet
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... C bus interface This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007. All rights reserved. MAPBGA–256 17mm x 17mm ® Document Number: MCF54455 Rev. 0, 09/2007 MCF54455 TEPBGA–360 23mm x 23mm ...
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MCF5445x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4 2 Ordering Information ...
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... Phase locked loop module RNG – Random Number Generator RTC – Real time clock SSI – Synchronous Serial Interface USB OTG – Universal Serial Bus On-the-Go controller Figure 1. MCF54455 Block Diagram ® Microprocessor Data Sheet, Rev. 0 Oscillator PLL 2 FECs USB OTG PCI ...
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... MAPBGA ® Microprocessor Data Sheet, Rev. 0 MCF54453 MCF54454 MCF54455 • • • 266 MHz up to 133 MHz MHz up to 410 16 kBytes each 32 kBytes • • • — • — ...
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... MCF54452 Microprocessor MCF54452VR266 MCF54453CVR200 MCF54453 Microprocessor MCF54453VR266 MCF54454CVR200 MCF54454 Microprocessor MCF54454VR266 MCF54455CVR200 MCF54455 Microprocessor MCF54455VR266 3 Hardware Design Considerations 3.1 Analog Power Filtering To further enhance noise isolation, an external filter is strongly recommended for the analog V VDD_RTC). The filter shown in Figure 2 capacitors should be placed as close to the dedicated analog V Do not implement the filter circuit using only capacitors ...
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Hardware Design Considerations 3.2 Oscillator Power Filtering Figure 3 shows an example for isolating the oscillator power supply from the I/O supply (EVDD) and ground. VDD_OSC VSS_OSC 3.3 Supply Voltage Sequencing Figure 4 shows situations in sequencing the I/O V ...
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... The following table lists all the MCF5445x pins grouped by function. The Dir column is the direction for the primary function of the pin only. Refer to Section 4, “Pin Assignments and Reset of the MCF5445x signals, consult the MCF54455 Reference Manual (MCF54455RM). In this table and throughout this document, a single signal within a group is designated without square brackets (i.e., FB_AD23), while designations for multiple signals within a group use brackets (i ...
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... EVDD B4, A4 — O EVDD B13 — O EVDD C2, D4, C3 — O EVDD C4 — O EVDD A2 — O EVDD EVDD B1 Freescale Semiconductor MCF54452 MCF54453 MCF54454 MCF54455 Y18 B17 A16 A17 AB17, AB21 L1, L4 L2, L3, M1–4, N1–2 T1–2 W1 Y1 W5, AA4, AB3 Y4 AA1 AA3 AB2 ...
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... Microprocessor Data Sheet, Rev. 0 Pin Assignments and Reset States MCF54452 MCF54450 MCF54453 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA — O EVDD A3 — I/O EVDD — C11, D11, A10, B10, J4, G2, G3, — I/O EVDD K14–13, J15–13, D12, C12, B12, H13– ...
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... EVDD H4 — O EVDD J1, J2 — O EVDD J3 Freescale Semiconductor MCF54452 MCF54453 MCF54454 MCF54455 360 TEPBGA L22 M22 L20, M20 L21, K22, K21, K20, J20, J19, J21, J22, H20, G22, G21, G20, G19, F22, F21, F20 H21, E21 H22, E22 N21 M21 N20 ...
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... VDD — O USB E5 VDD USB B3 VDD — O EVDD — — O EVDD — MCF54452 MCF54453 MCF54454 MCF54455 Y11 W11 AB12 W20 Y22 AB18 AA18 W14 AB15 AA15, Y15 AA17 Y17 W17 AB19 Y19, W18 AA19 Y20 AA21 AA22 A14 A15 AA2 ...
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... SBF_CS — — — SBF_CK — SBF_DI — SBF_DO — ® Microprocessor Data Sheet, Rev. 0 MCF54452 MCF54450 MCF54453 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA — O EVDD — — O EVDD — — I EVDD — — I EVDD — — I EVDD J16 — ...
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... TMS — TRST — Test — — — — ® Microprocessor Data Sheet, Rev. 0 Pin Assignments and Reset States MCF54452 MCF54450 MCF54453 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA — I EVDD — — O EVDD — — I EVDD — — O EVDD — ...
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... Microprocessor Data Sheet, Rev. 0 MCF54452 MCF54450 MCF54453 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA — — — E6–12, F5, F12 D6, D8, D14, F4, H4, N4, R4, W4, W7, W8, W12, — — — G5, G12, H5, H12, D13, D19, G8, J5, J12, K5, K12, G11, G14, G16, J7, L5– ...
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Pinout—256 MAPBGA The pinout for the MCF54450 and MCF54451 packages are shown below FB_BE/ FB_BE/ A VSS FB_OE FB_TS BWE0 BWE2 USB_ FB_BE/ FB_BE/ B FB_TA FB_R/W VBUS_ BWE1 BWE3 OC PST FB_AD C ...
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... Pin Assignments and Reset States 4.3 Pinout—360 TEPBGA The pinout for the MCF54452, MCF54453, MCF54454, and MCF54455 packages are shown below PCI_ PCI_ PCI_ PCI_ PCI_ A GND REQ0 AD10 AD11 AD13 SERR PCI_ PCI_ PCI_ PCI_ PCI_ PCI_ ...
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... Electrical Characteristics This document contains electrical specification tables and reference timing diagrams for the MCF54455 microprocessor. This section contains detailed information on DC/AC electrical characteristics and AC timing specifications. The electrical specifications are preliminary and from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle ...
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Electrical Characteristics 5.2 Thermal Characteristics Characteristic Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature 1 θ and Ψ parameters are simulated in conformance ...
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constant pertaining to the particular part. K can be determined from for a known T . Using this value of K, the values for any value 5.3 ESD Protection ...
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... There are three PV PV input Refer to the MCF54455 Reference Manual signals description chapter for pins having weak internal pull-up devices. 3 This parameter is characterized before qualification rather than 100% tested. 4 All functional non-supply pins are internally clamped Input must be current limited to the value specified ...
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Input Clock (CLKIN) Num Characteristic 1 PLL Reference Frequency Range Crystal reference External reference 2 Core/System Frequency Core/System Clock Period × PFDR) 19 VCO Frequency ( vco ref Crystal Start-up Time 4 EXTAL Input High ...
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Electrical Characteristics Table 10. PLL Electrical Characteristics (continued) Num Characteristic 13 Discrete load capacitance for XTAL Discrete load capacitance for EXTAL 14 Frequency un-LOCK Range 15 Frequency LOCK Range CLKOUT Period Jitter, Peak-to-peak Jitter (Clock edge ...
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CLKIN RESET RSTOUT Configuration Overrides*: (BOOTMOD[1:0], Override pins]) Figure 8. RESET and Configuration Override Timing 5.7 FlexBus Timing Specifications A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices maximum ...
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Electrical Characteristics FB_CLK FB_A[23:0] FB_AD[31:0] FB_R/W FB_TS FB_TSIZ[1:0] FB_CSn, FB_BSn FB_OE FB_TA MCF5445x ColdFire 24 FB1 A[23:0] FB2 FB5 DATA FB4 TSIZ[1:0] FB5 FB4 Figure 9. FlexBus Read Timing ® Microprocessor Data Sheet, Rev. 0 FB3 Freescale Semiconductor ...
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FB_CLK FB_A[23:0] FB_AD[31:0] FB_R/W FB_TS FB_TSIZ[1:0] FB_CSn, FB_BSn FB_OE FB_TA 5.8 SDRAM AC Timing Characteristics The following timing numbers must be followed to properly latch or drive data onto the SDRAM memory bus. All timing numbers are relative to the ...
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Electrical Characteristics Table 13. SDRAM Timing Specifications (continued) Num Characteristic DD7 Data and Data Mask Output Setup (DQ-->DQS) Relative to DQS (DDR Write Mode) DD8 Data and Data Mask Output Hold (DQS-->DQ) Relative to DQS (DDR Write Mode) DD9 Input ...
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SD_CLK SD_CLK SD_CSn,SD_WE, SD_RAS, SD_CAS DD4 SD_A[13:0] SD_DM3/SD_DM2 SD_DQS3/SD_DQS2 SD_D[31:24]/SD_D[23:16] MCF5445x ColdFire Freescale Semiconductor DD1 DD2 DD5 CMD DD6 ROW COL WD1 WD2 WD3 WD4 Figure 11. DDR Write Timing ® Microprocessor Data Sheet, Rev. 0 Electrical Characteristics DD3 DD7 ...
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Electrical Characteristics SD_CLK SD_CLK SD_CSn,SD_WE, SD_RAS, SD_CAS SD_A[13:0] SD_DQS3/SD_DQS2 D[31:24]/D[23:16] SD_DQS3/SD_DQS2 D[31:24]/D[23:16] 5.9 PCI Bus Timing Specifications The PCI bus on the device is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Refer to ...
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Table 14. PCI Timing Specifications Num P6 PCI_REQ[3:0]/PCI_GNT[3:0] — output valid P7 All PCI signals — output hold 1 The PCI bus operates at the CLKIN frequency. All timings are relative to the input clock, CLKIN. 2 All PCI signals ...
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Electrical Characteristics GND GND - 0.5V GND - 1.0V Figure 14. Overshoot and Undershoot Limits 5.10 ULPI Timing Specifications The ULPI interface is fully compliant with the industry standard UTMI+ ...
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USB_CLKIN ULPI_DIR / ULPI_NXT (Control Input) ULPI_DATA[7:0] (Data Input) ULPI_STP (Control Output) ULPI_DATA[7:0] (Data Output) 5.11 SSI Timing Specifications This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are ...
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Electrical Characteristics Num Description S11 SSI_BCLK cycle time S12 SSI_BCLK pulse width high / low S13 SSI_FS input setup before SSI_BCLK S14 SSI_FS input hold after SSI_BCLK S15 SSI_BCLK to SSI_TXD / SSI_FS output valid S16 SSI_BCLK to SSI_TXD / ...
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SSI_BCLK (Input) S15 SSI_FS (Output) SSI_FS (Input) S15 SSI_TXD SSI_RXD 2 5. Timing Specifications 2 Table 18 lists specifications for the I Table 18. I Num I1 Start condition hold time I2 Clock low period I3 I2C_SCL/I2C_SDA rise ...
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Electrical Characteristics 2 Table 19 Output Timing Specifications between SCL and SDA (continued) Num 1 I6 Clock high time 1 I7 Data setup time 1 I8 Start condition setup time (for repeated start condition only Stop ...
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RXCLK (Input) RXD[n:0] RXDV, RXER Figure 19. MII Receive Signal Timing Diagram 5.13.2 Transmit Signal Timing Specifications Num Characteristic — TXCLK frequency E5 TXCLK to TXD[n:0], TXEN, TXER invalid E6 TXCLK to TXD[n:0], TXEN, TXER valid E7 TXCLK pulse width ...
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Electrical Characteristics CRS, COL 5.13.4 MII Serial Management Timing Specifications Table 23. MII Serial Management Channel Signal Timing Num Characteristic E10 MDC cycle time E11 MDC pulse width E12 MDC to MDIO output valid E13 MDC to MDIO output invalid ...
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... The timings of the various ATA data transfer modes are determined by a set of timing equations described in the ATA section of the MCF54455 Reference Manual. These timing equations must be fulfilled for the ATA host to meet timing. provides implementation specific timing parameters necessary to complete the timing equations. ...
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Electrical Characteristics Table 26. DSPI Module AC Timing Specifications Name Characteristic DS10 DSPI_SCK to DSPI_SOUT invalid DS11 DSPI_SIN to DSPI_SCK input setup DS12 DSPI_SCK to DSPI_SIN input hold DS13 DSPI_SS active to DSPI_SOUT driven DS14 DSPI_SS inactive to DSPI_SOUT not ...
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DSPI_SS DSPI_SCK (DCTARn[CPOL DSPI_SCK (DCTARn[CPOL DSPI_SOUT DSPI_SIN Figure 24. DSPI Classic SPI Timing — Slave Mode 5.17 SBF Timing Specifications The Serial Boot Facility (SBF) provides a means to read configuration information and system boot code ...
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Electrical Characteristics SBF_CS SBF_CK SBF_DI SBF_DO 5.18 General Purpose I/O Timing Specifications Num G1 FB_CLK High to GPIO Output Valid G2 FB_CLK High to GPIO Output Invalid G3 GPIO Input Valid to FB_CLK High G4 FB_CLK High to GPIO Input ...
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JTAG and Boundary Scan Timing Num J1 TCLK Frequency of Operation J2 TCLK Cycle Period J3 TCLK Clock Pulse Width J4 TCLK Rise and Fall Times J5 Boundary Scan Input Data Setup Time to TCLK Rise J6 Boundary Scan ...
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Electrical Characteristics TCLK V IL Data Inputs Data Outputs Data Outputs Data Outputs TCLK V IL TDI TMS TDO TDO TDO TCLK TRST MCF5445x ColdFire 42 J5 Input Data Valid Figure 28. Boundary Scan (JTAG) Timing J9 ...
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Debug AC Timing Specifications Table 30 lists specifications for the debug AC timing parameters shown in Num D0 PSTCLK cycle time D1 PSTCLK rising to PSTDDATA valid D2 PSTCLK rising to PSTDDATA invalid D3 DSI-to-DSCLK setup 1 D4 DSCLK-to-DSO ...
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... Use these numbers in the web page’s keyword search engine to find the latest package outline drawings. Device MCF54450 MCF54451 MCF54452 MCF54453 MCF54454 MCF54455 7 Product Documentation Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire. 8 Revision History Table 32 summarizes revisions to this document ...
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MCF5445x ColdFire Freescale Semiconductor THIS PAGE INTENTIONALLY BLANK ® Microprocessor Data Sheet, Rev ...
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... Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MCF54455 Document Number: Rev. 0 09/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...