MCF54455CVR200 Freescale Semiconductor, MCF54455CVR200 Datasheet - Page 22

• Manufacturer Part Number: MCF54455CVR200
• Description: IC MPU 32BIT 200MHZ 360TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF5445xr

Specifications of MCF54455CVR200

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 132
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 360-TEPBGA
• Processor Series: MCF544x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 16 KB
• Data Ram Size: 32 KB
• Interface Type: I2C, SPI, SSI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M54455EVB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 16 Channel
• On-chip Dac: 16 bit, 16 Channel
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• For Use With: M54455EVB - BOARD EVAL FOR MCF5445X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical Characteristics
5.6
Table 11
22
1
2
3
4
5
6
7
Num
1
2
The minimum system frequency is the minimum input clock divided by the maximum low-power divider (16 MHz ÷ 32,768).
When the PLL is enabled, the minimum system frequency (f
reference only.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via PLL V
percentage for a given interval.
This parameter is guaranteed by characterization before qualification rather than 100% tested. Applies to external clock
Proper PC board layout procedures must be followed to achieve specifications.
This parameter is guaranteed by design rather than 100% tested.
This specification is the PLL lock time only and does not include oscillator start-up time.
C
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
12
13
14
15
17
Num
R1
S_PCB
RESET and Configuration Override data lines are synchronized internally. Setup and hold times must be met only if
recognition on a particular clock is required.
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously
to the system. Thus, RESET must be held a minimum of 100 ns.
R2
R3
R4
R5
R6
R7
R8
1
lists specifications for the reset timing parameters shown in
Crystal capacitive load
Discrete load capacitance for XTAL
Discrete load capacitance for EXTAL
Frequency un-LOCK Range
Frequency LOCK Range
CLKOUT Period Jitter,
Reset Timing Specifications
RESET valid to CLKIN (setup)
CLKIN to RESET invalid (hold)
RESET valid time
CLKIN to RSTOUT valid
RSTOUT valid to Configuration Override inputs valid
Configuration Override inputs valid to RSTOUT invalid (setup)
Configuration Override inputs invalid after RSTOUT invalid (hold)
RSTOUT invalid to Configuration Override inputs High Impedance
is the measured PCB stray capacitance on EXTAL and XTAL.
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
2
Characteristic
Table 10. PLL Electrical Characteristics (continued)
3, 4, 7
Table 11. Reset and Configuration Override Timing
MCF5445x ColdFire
Measured at f
Characteristic
DD
, EV
DD
, and V
SYS
®
Microprocessor Data Sheet, Rev. 6
Max
SS
and variation in crystal oscillator frequency increase the Cjitter
sys
) is 150 MHz.
Figure
C
Symbol
C
L_EXTAL
C
L_XTAL
f
f
C
LCK
jitter
UL
L
8.
Min
1.5
Value
20
—
—
Min.
9
5
0
0
-4.0
-2.0
See crystal spec
—
—
—
C
C
C
2 × (C
Max
S_EXTAL
S_XTAL
10
Value
S_PCB
—
—
—
—
—
—
Freescale Semiconductor
Max.
1
TBD
4.0
2.0
10
L
)
-
6
-
-
CLKIN cycles
CLKIN cycles
CLKIN cycles
% FB_CLK
% FB_CLK
Unit
ns
ns
ns
ns
ns
% f
% f
Unit
pF
sys
sys
sys
.