C8051F537-IM Silicon Laboratories Inc, C8051F537-IM Datasheet - Page 68

• Manufacturer Part Number: C8051F537-IM
• Description: IC 8051 MCU 2K FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F53xr

Specifications of C8051F537-IM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-QFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1400

C8051F52x/F52xA/F53x/F53xA
SFR Definition 4.9. ADC0TK: ADC0 Tracking Mode Select
68
Bits7–4: AD0PWR3–0: ADC0 Burst Power-Up Time.
Bits3–2: AD0TM1–0: ADC0 Tracking Mode Select Bits.
Bits1–0: AD0TK1–0: ADC0 Post-Track Time.
R/W
Bit7
For BURSTEN = 0:
ADC0 power state controlled by AD0EN.
For BURSTEN = 1 and AD0EN = 1;
ADC0 remains enabled and does not enter the very low power state.
For BURSTEN = 1 and AD0EN = 0:
ADC0 enters the very low power state as specified in Table 2.3 on page 29 and is enabled
after each convert start signal. The Power Up time is programmed according to the following
equation:
00: Reserved.
01: ADC0 is configured to Post-Tracking Mode.
10: ADC0 is configured to Pre-Tracking Mode.
11: ADC0 is configured to Dual-Tracking Mode (default).
Post-Tracking time is controlled by AD0TK as follows:
00: Post-Tracking time is equal to 2 SAR clock cycles + 2 FCLK cycles.
01: Post-Tracking time is equal to 4 SAR clock cycles + 2 FCLK cycles.
10: Post-Tracking time is equal to 8 SAR clock cycles + 2 FCLK cycles.
11: Post-Tracking time is equal to 16 SAR clock cycles + 2 FCLK cycles.
AD0PWR
R/W
Bit6
AD0PWR
=
Tstartup
---------------------- 1
R/W
Bit5
200ns
–
R/W
Bit4
or
Tstartup
Rev. 1.3
R/W
Bit3
AD0TM
=
R/W
Bit2

AD0PWR
R/W
Bit1
+
AD0TK
1
(bit addressable)
200ns
R/W
Bit0
SFR Address:
Reset Value
11111111
0xBA