C8051F537-IM Silicon Laboratories Inc, C8051F537-IM Datasheet - Page 183
![IC 8051 MCU 2K FLASH 20QFN](/photos/12/25/122567/silicon_laboratories_inc-20-qfn_sml.jpg)
C8051F537-IM
Manufacturer Part Number
C8051F537-IM
Description
IC 8051 MCU 2K FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F53xr
Specifications of C8051F537-IM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.25 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-QFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1400
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F537-IM
Manufacturer:
Silicon Labs
Quantity:
135
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18.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
18.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal INT0
is active as defined by bit IN0PL in register IT01CF (see Section “10.5. External Interrupts” on page 104 for
details on the external input signals INT0 and INT0).
/INT0
T0
Crossbar
Pre-scaled Clock
SYSCLK
IN0PL
GATE0
Figure 18.2. T0 Mode 2 Block Diagram
XOR
0
1
TR0
C8051F52x/F52xA/F53x/F53xA
M
T
H
2
CKCON
T
M
2
L
0
1
M
T
1
M
T
0
C
S
A
1
Rev. 1.3
S
C
A
0
G
A
T
E
1
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(8 bits)
(8 bits)
TH0
TL0
N
1
P
L
I
N
1
S
L
2
I
INT01CF
N
S
1
L
1
I
N
S
1
L
0
I
N
P
0
L
I
Reload
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
I
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
Interrupt
183
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