C8051F537-IM Silicon Laboratories Inc, C8051F537-IM Datasheet - Page 24
![IC 8051 MCU 2K FLASH 20QFN](/photos/12/25/122567/silicon_laboratories_inc-20-qfn_sml.jpg)
C8051F537-IM
Manufacturer Part Number
C8051F537-IM
Description
IC 8051 MCU 2K FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F53xr
Specifications of C8051F537-IM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.25 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-QFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1400
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F537-IM
Manufacturer:
Silicon Labs
Quantity:
135
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C8051F52x/F52xA/F53x/F53xA
1.9. Port Input/Output
C8051F52x/F52xA/F53x/F53xA devices include up to 16 I/O pins. Port pins are organized as two byte-
wide ports. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be
configured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or
open-drain operation. The “weak pullups” that are fixed on typical 8051 devices may be globally disabled
to save power.
The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip coun-
ter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on the
port pins using the Crossbar control registers. This allows the user to select the exact mix of general-pur-
pose port I/O, digital, and analog resources needed for the application.
24
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
T0, T1
P0
P1
UART
CP0
PCA
SPI
LIN
(P0.0-P0.7)
(P1.0-P1.7*)
Figure 1.9. Port I/O Functional Block Diagram
2
2
2
4
7
2
8
8
Rev. 1.3
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
8
8
P0MASK, P0MATCH
P1MASK, P1MATCH
Registers
Cells
Cells
I/O
I/O
P0
P1
*Available in
PnMDIN Registers
devices
PnMDOUT,
'F53x/'F53xA
P0.0
P0.7
P1.0*
P1.7*
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