C8051F537-IM Silicon Laboratories Inc, C8051F537-IM Datasheet - Page 187
![IC 8051 MCU 2K FLASH 20QFN](/photos/12/25/122567/silicon_laboratories_inc-20-qfn_sml.jpg)
C8051F537-IM
Manufacturer Part Number
C8051F537-IM
Description
IC 8051 MCU 2K FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F53xr
Specifications of C8051F537-IM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.25 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-QFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1400
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F537-IM
Manufacturer:
Silicon Labs
Quantity:
135
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SFR Definition 18.3. CKCON: Clock Control
Bit7–6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1–0: SCA1–SCA0: Timer 0/1 Prescale Bits.
R/W
Bit7
—
RESERVED. Read = 0b; Must write 0b.
T2MH: Timer 2 High Byte Clock Select.
This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8-
bit timer mode. T2MH is ignored if Timer 2 is in any other mode.
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
T2ML: Timer 2 Low Byte Clock Select.
This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Counter/Timer 0 uses the system clock.
These bits control the division of the clock supplied to Timer 0 and Timer 1 if configured to
use prescaled clock inputs.
Note: External clock divided by 8 is synchronized with
the system clock.
SCA1
0
0
1
1
R/W
Bit6
—
SCA0
0
1
0
1
T2MH
R/W
Bit5
System clock divided by 12
System clock divided by 4
System clock divided by 48
External clock divided by 8
T2ML
R/W
Bit4
C8051F52x/F52xA/F53x/F53xA
Prescaled Clock
Rev. 1.3
T1M
R/W
Bit3
T0M
R/W
Bit2
SCA1
R/W
Bit1
SFR Address:
SCA0
R/W
Bit0
00000000
Reset Value
0x8E
187
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