MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 94

IC MCU 8BIT 1K RAM 68-PLCC

MCHC11F1CFNE3

Manufacturer Part Number
MCHC11F1CFNE3
Description
IC MCU 8BIT 1K RAM 68-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MCHC11F1CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
30
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
A/d Inputs
8-Channel, 8-Bit
Eeprom Memory
512 Bytes
Input Output
30
Interface
SCI/SPI
Memory Type
EPROM
Number Of Bits
8
Package Type
68-pin PLCC
Programmable Memory
0 Bytes
Timers
3-16-bit
Voltage, Range
3-5.5 V
Controller Family/series
68HC11
No. Of I/o's
30
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC11F
Core
HC11
Data Bus Width
8 bit
Program Memory Size
512 B
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
RoHS Compliant part

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OR — Overrun Error Flag
NF — Noise Error Flag
FE — Framing Error
Bit 0 — Not implemented
7.6.5 Baud Rate Register
BAUD — Baud Rate
TCLR — Clear Baud Rate Counters (Test)
SCP[1:0] — SCI Baud Rate Prescaler Selects
7-8
RESET:
SCP1
OR is set if a new character is received before a previously received character is read
from SCDR. Clear the OR flag by reading SCSR and then reading SCDR.
NF is set if majority sample logic detects anything other than a unanimous decision.
Clear NF by reading SCSR and then reading SCDR.
FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by
reading SCSR and then reading SCDR.
Always reads zero
Use this register to select different baud rates for the SCI system. The SCP[1:0] bits
select the prescaler rate for the SCR[2:0] bits. Together, these five bits provide multi-
ple baud rate combinations for a given crystal frequency. Normally, this register is writ-
ten once during initialization. The prescaler is set to its fastest rate by default out of
reset, and can be changed at any time. Refer to Table 7-1 and Table 7-2 for normal
baud rate selections.
Refer to the SCI baud rate generator block diagram.
0
0
1
1
Prescaler
0 = No overrun
1 = Overrun detected
0 = Unanimous decision
1 = Noise detected
0 = Stop bit detected
1 = Zero detected
SCP0
TCLR
Bit 7
0
1
0
1
0
Divide Internal
Clock By
6
0
Table 7-1 Baud Rate Prescaler Selection
Freescale Semiconductor, Inc.
13
1
3
4
For More Information On This Product,
SERIAL COMMUNICATIONS INTERFACE
SCP1
5
0
Go to: www.freescale.com
62500
20833
15625
4800
4.0
SCP0
4
0
4.9152
76800
25600
19200
5907
RCKB
3
0
Crystal Frequency (MHz)
125000
41667
31250
9600
8.0
SCR2
U
2
187500
62500
46875
14423
SCR1
12.0
U
1
TECHNICAL DATA
25000
83332
62500
19200
SCR0
16.0
Bit 0
U
MC68HC11F1
312500
104165
78125
24000
$102B
20.0

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