MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 119

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

9.4.1 Timer Interrupt Mask Register 2
TMSK2 — Timer Interrupt Mask Register 2
TOI — Timer Overflow Interrupt Enable
RTII — Real-Time Interrupt Enable
PAOVI — Pulse Accumulator Overflow Interrupt Enable
PAII — Pulse Accumulator Input Edge
PR[1:0] — Timer Prescaler Select
TECHNICAL DATA
RESET:
The clock source for the RTI function is a free-running clock that cannot be stopped or
interrupted except by reset. This clock causes the time between successive RTI time-
outs to be a constant that is independent of the software latencies associated with flag
clearing and service. For this reason, an RTI period starts from the previous time-out,
not from when RTIF is cleared.
Every time-out causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt
request is generated. After reset, one entire RTI period elapses before the RTIF flag
is set for the first time. Refer to the TMSK2, TFLG2, and PACTL registers.
This register contains the real-time interrupt enable bits.
Refer to 9.6 Pulse Accumulator.
Refer to 9.6 Pulse Accumulator.
Refer to Table 9-4.
RTR[1:0]
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to one
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF set to one
0 0
0 1
1 0
1 1
Bit 7
TOI
0
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
E = 1 MHz
16.384 ms
32.768 ms
65.536 ms
8.192 ms
RTII
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
PAOVI
Table 9-4 RTI Rate Selection
5
0
Go to: www.freescale.com
E = 2 MHz
16.384 ms
32.768 ms
4.096 ms
8.192 ms
TIMING SYSTEM
PAII
4
0
NOTE
E = 3 MHz
10.923 ms
21.845 ms
2.731 ms
5.461 ms
—
0
3
—
2
0
E = 4 MHz
16.384 ms
2.048 ms
4.096 ms
8.192 ms
PR1
1
0
Bit 0
PR0
E = X MHz
0
(2
(2
(2
(2
13
14
15
16
/E)
/E)
/E)
/E)
$1024
9-13